A performance analytical model for Network-on-Chip with constant service time routers

Nikitin, Nikita; Cortadella, Jordi

doi:10.1145/1687399.1687506

Cited by 33 publications

(20 citation statements)

References 8 publications

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“…Different proposals focus on the queueing theory to model on-chip networks. Nikitin and Cortadella [26] presented analytical model that focuses on QoS assurance. However, it assumes that the NoC has an underlying synchronous behavior with constant service time routers, thus it is not suitable for optimization using the well known DVFS-based actuators.…”

Section: Noc-based Power-performance Optimizationsmentioning

confidence: 99%

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A control-based methodology for power-performance optimization in NoCs exploiting DVFS

Zoni

Terraneo

Fornaciari

2015

Journal of Systems Architecture

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a b s t r a c tNetworks-on-Chip (NoCs) are considered a viable solution to fully exploit the computational power of multi-and many-cores, but their non negligible power consumption requires ad hoc power-performance design methodologies. In this perspective, several proposals exploited the possibility to dynamically tune voltage and frequency for the interconnect, taking steps from traditional CPU-based power management solutions. However, the impact of the actuators, i.e. the limited range of frequencies for a PLL (Phase Locked Loop) or the time to increase voltage and frequency for a Dynamic Voltage and Frequency Scaling (DVFS) modules, are often not carefully accounted for, thus overestimating the benefits. This paper presents a control-based methodology for the NoC power-performance optimization exploiting the Dynamic Frequency Scaling (DFS). Both timing and power overheads of the actuators are considered, thanks to an ad hoc simulation framework. Moreover the proposed methodology eventually allows for user and/or OS interactions to change between different high level power-performance modes, i.e. to trigger performance oriented or power saving system behaviors. Experimental validation considered a 16-core architecture comparing our proposal with different settings of threshold-based policies. We achieved a speedup up to 3 for the timing and a reduction up to 33.17% of the power ⁄ time product against the best threshold-based policy. Moreover, our best control-based scheme provides an averaged power-performance product improvement of 16.50% and 34.79% against the best and the second considered threshold-based policy setting.

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Section: Noc-based Power-performance Optimizationsmentioning

confidence: 99%

“…The solution follows the classic queue theory, while the router serving time model has been derived from real data. However, the methodology relies on exponential distribution for flit arrival times which cannot in general be guaranteed in NoCs [26], and does not account for run-time frequency variations.…”

Section: Noc-based Power-performance Optimizationsmentioning

confidence: 99%

A control-based methodology for power-performance optimization in NoCs exploiting DVFS

Zoni

Terraneo

Fornaciari

2015

Journal of Systems Architecture

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“…However, exiting analysis methodologies [2,5,15,16,19,10,9,13] are based on the assumption that NoCs are homogeneous. Figure 1 illustrates the delay evaluation of a heterogeneous NoC for two existing extreme analysis methodologies: single-VC [2,5,15,16] and "infinite-VCs", i.e. assuming that virtual channels are always available for any flow [6,12,1].…”

Section: Introductionmentioning

confidence: 99%

Delay analysis of wormhole based heterogeneous NoC

Ben-Itzhak

Cidon

Kolodny

2011

Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip

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We introduce a novel evaluation methodology to analyze the delay of a wormhole routing based NoC with variable link capacities and a variable number of virtual channels per link. This methodology can be utilized to analyze different heterogeneous NoC architectures and traffic scenarios for which no analysis framework has been developed before. In particular, it can replace computationally-extensive simulations at the inner-loop of the link capacities and virtual channels allocation steps of the NoC topology optimization process. Our analysis introduces a set of implicit equations which can be efficiently solved iteratively. We demonstrate the accuracy of our approximation by comparing the analysis results to a simulation model for several use-cases and synthetic examples. In addition, we compare the analysis with simulation results for a chip-multi-processor (CMP) using SPLASH-2 and PARSEC traces for both homogeneous and heterogeneous NoC configurations.

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“…For simplicity, we assume that the packets have a fixed size of m (flits) as in [41]. However, this assumption can be relaxed to cover arbitrary packet length distribution.…”

Section: Proposed Noc Analytical Model 231 Basic Assumptions and Nomentioning

confidence: 99%

“…Therefore, most of the previous efforts are based on queuing models to evaluate the NoC delay. [37,41]. Several works have been proposed to improve the estimation accuracy by generalizing the arrival and service time distributions.…”

Section: Introductionmentioning

confidence: 99%

High performance network-on-chips (NoCs) design : performance modeling, routing algorithm and architecture optimization

Qian¹

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TABLE OF CONTENTS Title Page i Authorization Page ii Signature Page iiiAcknowledgments iv Table of Contents v List of Figures ix List of Tables xiiiAbstract xiv Therefore, fast and accurate analytical models for NoC-based multicore performance evaluation are strongly desired to better explore the design space. For this purpose, we propose a machine learning based latency regression model to evaluate the NoC designs with respect to different configurations before the system is built or taped-out. Then, for high performance NoC designs, we tackle one of the most important problems, i.e., the routing algorithms design with different design constraints and objectives. For avoiding temperature hotspots, a thermal-aware routing algorithm is proposed to achieve an even temperature profile for application-specific Network-on-chips (NoCs). For improving the reliability, a routing algorithm to achieve maximum performance under fault is proposed. Finally, in the architecture level, we propose two new NoC structures using bi-directional links for the performance optimization. In particular, we propose a flit-level speedup scheme to enhance the network-on-chip(NoC) performance utilizing bidirectional channels. In addition to the traditional efforts on allowing flits of different packets using the idling internal and external bandwidth of the bidirectional channel, our proposed flit-level speedup scheme also allows flits within the same packet to be transmitted simultaneously on the bi-directional channel.We also propose a flexible NoC architecture which takes advantage of a dynamic distributed routing algorithm and improves the NoC communication performance with minimal energy overhead. This proposed NoC architecture exploits the selfreconfigurable bidirectional channels to increase the effective bandwidth and uses express virtual paths, as well as localized hub routers, to bypass some intermediate nodes at run time in the network. From the simulation results on both synthetic traffic and real workload traces, significantly performance improvement in terms of latency and throughput can be achieved.

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A performance analytical model for Network-on-Chip with constant service time routers

Cited by 33 publications

References 8 publications

A control-based methodology for power-performance optimization in NoCs exploiting DVFS

A control-based methodology for power-performance optimization in NoCs exploiting DVFS

Delay analysis of wormhole based heterogeneous NoC

High performance network-on-chips (NoCs) design : performance modeling, routing algorithm and architecture optimization

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