A performance analysis of Pentium processor systems

Characterization and Parallelization of Decision-Tree Induction

“…Figure 2 shows the IPC for the superscalar processor for the L2 hit time # [5,8,11,14,17,20] cycles. As expected, increasing the L2 hit time does increase the performance benefit of a larger L1 cache; for example, for the german-org data set, when the L2 cache has a five-cycle hit time, increasing the L1-cache size from 1 to 512 Kbyte increases the IPC 10 0 from 2.23 to 2.45, while for a 20-cycle L2 cache the increase is 62 0 from 1.51 to 2.45.…”

“…Previous work on characterizing commercial applications has focused primarily on the SQL database queries used in the TPC-B, TPC-C, and TPC-D benchmark programs [13]. Some exceptions are examining the characteristics of the AltaVista Web search engine [2], several desktop applications running under Windows NT [4,14], the Apache Web server [8], and several papers in [11].…”

Performance evaluation of configurable hardware features on the AMD-K5

“…If the first instance of an address is a store, there is a high probability that there are more loads and stores to the same address and to the same cache line. The performance improvement on Unix based applications should be even greater, based on the information from Bekerman and Mendelson [4]. Their performance evaluation showed Unix applications to have better spatial and temporal locality for their memory references than Windows applications.…”

“…Bekerman and Mendelson [4] used the Pentium performance monitoring counters and some software monitoring to measure how the Pentium was performing on some Unix and Windows benchmarks. This is slightly different from the approach in this paper because they were not changing features inside the processor but merely measuring how the standard mode of the processor was performing.…”