A Partially Binarized Hybrid Neural Network System for Low-Power and Resource Constrained Human Activity Recognition

Vita, Antonio De; Russo, Alessandro; Pau, Danilo; Benedetto, Luigi Di; Rubino, Alfredo; Licciardo, Gian Domenico

doi:10.1109/tcsi.2020.3011984

Cited by 21 publications

(15 citation statements)

References 42 publications

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“…Namely, 391 µW/MHz and 144.4 µW/MHz. Considering that conventional human activity recognition systems operates at 50 Hz [4,5], a dynamic power dissipation less than 1 mW can be considered, which is not sensed by the Xilinx tool since it is much lower than the 70 mW of the quiescent power dissipation of the employed FPGA.…”

Section: Synthesis and Implementation Resultsmentioning

confidence: 99%

“…Additionally, all the activations have been binarized, and the activation functions have been reduced to [4]:…”

Section: The Fcn Modelmentioning

confidence: 99%

“…The monitoring and interpretation of static and dynamic behavior of the human body are very attractive for a number of applications ranging from biomedical to industrial and automotive [1,2]. Although the capability to classify human postures can be considered a specific subset of the Human Activity Recognition (HAR) [3][4][5], it requires specific technological solutions, very different from HAR, and is very important in peculiar application fields. To improve the quality of life, for example, which can be significantly compromised by prolonged poor sitting and laying postures [6][7][8], causing serious health problems such as pressure ulcers, cervical and back diseases, and complex muscle and skeletal deformations.…”

Section: Introductionmentioning

confidence: 99%

“…Moreover, despite of the reduced number of sensors, the overall extension of the system is not negligible, considering the processing unit and the connections between this and the sensors. On the other hand, other solutions exhibit a computational load scarcely compatible with embedded systems with autonomous power supplies [3][4][5].…”

Section: Introductionmentioning

confidence: 99%

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A Resource Constrained Neural Network for the Design of Embedded Human Posture Recognition Systems

et al. 2021

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A custom HW design of a Fully Convolutional Neural Network (FCN) is presented in this paper to implement an embeddable Human Posture Recognition (HPR) system capable of very high accuracy both for laying and sitting posture recognition. The FCN exploits a new base-2 quantization scheme for weight and binarized activations to meet the optimal trade-off between low power dissipation, a very reduced set of instantiated physical resources and state-of-the-art accuracy to classify human postures. By using a limited number of pressure sensors only, the optimized HW implementation allows keeping the computation close to the data sources according to the edge computing paradigm and enables the design of embedded HP systems. The FCN can be simply reconfigured to be used for laying and sitting posture recognition. Tested on a public dataset for in-bed posture classification, the proposed FCN obtains a mean accuracy value of 96.77% to recognize 17 different postures, while a small custom dataset has been used for training and testing for sitting posture recognition, where the FCN achieves 98.88% accuracy to recognize eight positions. The FCN has been prototyped on a Xilinx Artix 7 FPGA where it exhibits a dynamic power dissipation lower than 11 mW and 7 mW for laying and sitting posture recognition, respectively, and a maximum operation frequency of 47.64 MHz and 26.6 MHz, corresponding to an Output Data Rate (ODR) of the sensors of 16.50 kHz and 9.13 kHz, respectively. Furthermore, synthesis results with a CMOS 130 nm technology have been reported, to give an estimation about the possibility of an in-sensor circuital implementation.

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Section: Synthesis and Implementation Resultsmentioning

confidence: 99%

“…Additionally, all the activations have been binarized, and the activation functions have been reduced to [4]:…”

Section: The Fcn Modelmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A Resource Constrained Neural Network for the Design of Embedded Human Posture Recognition Systems

et al. 2021

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“… A new custom partial-binarization schema has been used for both the encoder and the decoder, to feature binarized weights and non-binarized activations for some selected layers.  The number of physical resources needed by the AE implementation has been limited thanks to a careful custom HW design rather than by reducing the number of layers [10]- [14].  This choice takes advantage of the low number of activations of the classifier and enables the possibility of sharing it with multiple AEs integrated into several sensors distributed on the apparatus under monitoring.…”

Section: Introductionmentioning

confidence: 99%

Low-Power Detection and Classification for In-Sensor Predictive Maintenance Based on Vibration Monitoring

et al. 2022

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In this work, a new custom design of an anomaly detection and classification system is proposed. It is composed of a convolutional Auto-Encoder (AE) hardware design to perform anomaly detection which cooperates with a mixed HW/SW Convolutional Neural Network (CNN) to perform the classification of detected anomalies. The AE features a partial binarization, so that the weights are binarized while the activations, associated to some selected layers, are non-binarized. This has been necessary to meet the severe area and energy constraints that allow it to be integrated on the same die as the MEMS sensors for which it serves as a neural accelerator. The CNN shares the feature extraction module with the AE, whereas a SW classifier is triggered by the AE when a fault is detected, working asynchronously to it. The AE has been mapped on a Xilinx Artix-7 FPGA, featuring an Output Data Rate (ODR) of 365 kHz and achieving a power dissipation of 333 W/MHz. Logic synthesis has targeted TSMC CMOS 65 nm, 90 nm, and 130 nm standard cells. Best results achieved highlight a power consumption of 138 μW/MHz with an area occupation of 0.49 mm 2 when real-time operations are set. These results enable the integration of the complete neural accelerator in the CMOS circuitry that typically sits with the inertial MEMS on the same silicon die. Comparisons with the related works suggest that the proposed system is capable of state-of-the-art performances and accuracy.

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A 0.8 mW TinyML-Based PDM-to-PCM Conversion for In-Sensor KWS Applications

Vitolo

Liguori

Benedetto

et al. 2023

Lecture Notes in Electrical Engineering

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A Partially Binarized Hybrid Neural Network System for Low-Power and Resource Constrained Human Activity Recognition

Cited by 21 publications

References 42 publications

A Resource Constrained Neural Network for the Design of Embedded Human Posture Recognition Systems

A Resource Constrained Neural Network for the Design of Embedded Human Posture Recognition Systems

Low-Power Detection and Classification for In-Sensor Predictive Maintenance Based on Vibration Monitoring

A 0.8 mW TinyML-Based PDM-to-PCM Conversion for In-Sensor KWS Applications

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