A parameterized NoC simulator using OMNet++

Al-Badi, Rahil Said; Al-Riyami, M; Alzeidi, Nasser

doi:10.1109/icumt.2009.5345363

Cited by 16 publications

(5 citation statements)

References 14 publications

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“…Once the scheduler can transmit the head-flit (depends on the capacity of the port`s outgress link), it sends a grant message to the in-port (4). In return, the in-port sends a credit message to the scheduler of the previous router (5) and also sends the head-flit to the out-port (6). Then, the scheduler sends it to the in-port of the next-router (7).…”

Section: A Hierarchical Routermentioning

confidence: 99%

HNOCS: Modular open-source simulator for Heterogeneous NoCs

Ben-Itzhak

Zahavi

Cidon

et al. 2012

2012 International Conference on Embedded Computer Systems (SAMOS)

105

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Section: A Hierarchical Routermentioning

confidence: 99%

HNOCS: Modular open-source simulator for Heterogeneous NoCs

Ben-Itzhak

Zahavi

Cidon

et al. 2012

2012 International Conference on Embedded Computer Systems (SAMOS)

105

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“…To date, the majority of fault-tolerant ASNoC designs have been evaluated using NoC simulators available in the literature [6]- [8]. These simulators, however, can only provide an estimate of parameters, which may not be accurate when the design is ported to an FPGA.…”

Section: Introductionmentioning

confidence: 99%

Fault-Tolerant Application-Specific Topology-Based NoC and Its Prototype on an FPGA

et al. 2021

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Application-Specific Networks-on-Chips (ASNoCs) are suitable communication platforms for meeting current application requirements. Interconnection links are the primary components involved in communication between the cores of an ASNoC design. The integration density in ASNoC increases with continuous scaling down of the transistor size. Excessive integration density in ASNoC can result in the formation of thermal hotspots, which can cause a system to fail permanently. As a result, faulttolerant techniques are required to address the permanent faults in interconnection links of an ASNoC design. By taking into account link faults in the topology, this paper introduces a fault-tolerant applicationspecific topology-based NoC design and its prototype on an FPGA. To place spare links in the ASNoC topology, a meta-heuristic algorithm based on Particle Swarm Optimization (PSO) is proposed. By taking link faults into account in ASNoC design, we also propose an application mapping heuristic and a tablebased fault-tolerant routing algorithm. Experiments are carried out for a specific link and any link fault in fault-tolerant topologies generated by our approach and approaches reported in the literature. For the experimentation, we used the multi-media applications Picture-in-Picture (PiP), Moving Pictures Expert Group (MPEG) -4, MP3Encoder, and Video Object Plane Decoder (VOPD). Experiments are run on software and hardware platforms. The static performance metric communication cost and the dynamic performance metrics network latency, throughput, and router power consumption are examined using software platform. In the hardware platform, the Field Programmable Gate Array (FPGA) is used to validate proposed fault-tolerant topologies and analyze performance metrics such as application runtime, resource utilization, and power consumption. The results are compared with the existing approaches, specifically Ring topology and its modified versions on both software and hardware platforms. The experimental results obtained from software and hardware platforms for a specific link and any link fault show significant improvements in performance metrics using our approach when compared with the related works in the literature.

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“…By running specific scenarios, these tools help to determine channel and buffer sizing, project routing and switching techniques, assess communication performance, specify packet format, and avoid starvation caused by deadlocks. NoC simulation tools have been adopted academically and by the industry in the last years [3,4,5,6,7,8,9,10,11,12,13,14,15]. However, most of these tools present a complex interface and require extra runtime and knowledge when explored together with hardware simulation tools.…”

Section: Introductionmentioning

confidence: 99%

A Multi-Agent-Based Network-on-Chip Simulator

Lima

Adamatti

Brião

et al. 2021

JICS

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Integrated systems have incorporated a variety of functionalities within the same chip, requiring on-chip communication mainly based on the Network-on-Chip (NoC) design paradigm. Complex systems may impose strict requirements concerning performance, power and reliability. Thus, the choice of proper routing algorithms to the on-chip communication for NoCs merits special attention. To assist designers to adjust communication parameters, implement routing algorithms, and check system correctness, simulators become powerful and cost-effective solutions. This article explores Multi-Agent System to develop a high level abstraction NoC simulation environment. The simulator allows designers to evaluate routing algorithms, test alternative configurations and message formats. The simulation provides important measurementssuch as rate of utilization of routers, network contention and delay in sending messages. As a case study, the XY and WF routing algorithms were modeled and analyzed. Results highlight the pros and cons of each algorithm, and outline the simulator overall performance.

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A parameterized NoC simulator using OMNet++

Cited by 16 publications

References 14 publications

HNOCS: Modular open-source simulator for Heterogeneous NoCs

HNOCS: Modular open-source simulator for Heterogeneous NoCs

Fault-Tolerant Application-Specific Topology-Based NoC and Its Prototype on an FPGA

A Multi-Agent-Based Network-on-Chip Simulator

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