A parallelized way to provide data encryption and integrity checking on a processor-memory bus

Elbaz,; Торрес,; Sassatelli,; Guillemin,; Bardouillet,; Martinez, Kirk

doi:10.1109/dac.2006.229264

Cited by 12 publications

(12 citation statements)

References 5 publications

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“…Such a solution allows reducing the cryptography latency overhead while maintaining a strong level of protection. Compared to [6,7], we rely on a more comprehensive security policy where developer can finely tune his/her cryptography needs. Then, this work also presents a feedback feature for security mechanisms (Section 4): that is to say how attacks are detected and how the update manager takes care of these information.…”

Section: Main Contributionsmentioning

confidence: 99%

Protection of heterogeneous architectures on FPGAs: An approach based on hardware firewalls

Cotret

Gogniat

Florez

2016

Microprocessors and Microsystems

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International audienceEmbedded systems are parts of our daily life and used in many fields. They can be found in smart-phones or in modern cars including GPS, light/rain sensors and other electronic assistance mechanisms.These systems may handle sensitive data (such as credit card numbers, critical information about thehost system and so on) which must be protected against external attacks as these data may be transmit-ted through a communication link where attackers can connect to extract sensitive information or injectmalicious code within the system. This work presents an approach to protect communications in multi-processor architectures. This approach is based on hardware security enhancements acting as firewalls.These firewalls filter all data going through the system communication bus and an additional flexiblecryptographic block aims to protect external memory from attacks. Benefits of our approach are demon-strated using a case study and some custom software applications implemented in a Field-ProgrammableGate Array (FPGA). Firewalls implemented in the target architecture allow getting a low-latency securitylayer with flexible cryptographic features. To illustrate the benefit of such a solution, implementations arediscussed for different MPSoCs implemented on Xilinx Virtex-6 FPGAs. Results demonstrate a reductionup to 33% in terms of latency overhead compared to existing effort

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Section: Main Contributionsmentioning

confidence: 99%

Protection of heterogeneous architectures on FPGAs: An approach based on hardware firewalls

Cotret

Gogniat

Florez

2016

Microprocessors and Microsystems

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“…Some other works on memory-bus encryption [13,14] mention hardware engines for bus encryption. [13] describes an engine called "Parallelized Encryption and Integrity Checking Engine (PE-ICE)", which guarantees the confidentiality and integrity of data exchanged between a system-on-chip (SoC) and its external memory. This approach is based on an existing block-encryption algorithm, to which the integrity checking capability is added.…”

Section: Previous Workmentioning

confidence: 99%

“…This approach is based on an existing block-encryption algorithm, to which the integrity checking capability is added. According to [13], it results in low performance overhead. In [14], a comprehensive survey on existing techniques for hardware engines which are used in bus encryption is presented.…”

Section: Previous Workmentioning

confidence: 99%

Memory Encryption for Smart Cards

Ege

Yalcin

2011

Smart Card Research and Advanced Applications

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Part 5: Implementations and Hardware Security 2International audienceWith the latest advances in attack methods, it has become increasingly more difficult to secure data stored on smart cards, especially on non-volatile memories (NVMs), which may store sensitive information such as cryptographic keys or program code. Lightweight and low-latency cryptographic modules are a promising solution to this problem. In this study, memory encryption schemes using counter (CTR) and XOR-Encrypt-XOR (XEX) modes of operation are adapted for the target application, and utilized using various implementations of the block ciphers AES and PRESENT. Both schemes are implemented with a block cipher-based address scrambling scheme, as well as a special write counter scheme in order to extend the lifetime of the encryption key in CTR-mode. Using the lightweight cipher PRESENT, it is possible to implement a smart card NVM encryption scheme with less than 6K gate equivalents and zero additional latency

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“…Later, [40] implements a trusted computing platform on top of the XOM architecture. Two related approaches, [22,69], provide a memory security solution by encrypting the memory and providing an integrity check. In [22], a Parallelized data Encryption and Integrity Checking Engine (PE-ICE) is described which adds memory integrity checking to a block encryption algorithm.…”

Section: Trustmentioning

confidence: 99%

“…Two related approaches, [22,69], provide a memory security solution by encrypting the memory and providing an integrity check. In [22], a Parallelized data Encryption and Integrity Checking Engine (PE-ICE) is described which adds memory integrity checking to a block encryption algorithm. Then in [69], a one-time pad is used in combination with a CRC-based integrity checker to secure the memory.…”

Section: Trustmentioning

confidence: 99%

Preventing integrated circuit piracy using reconfigurable logic barriers

Baumgarten

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A parallelized way to provide data encryption and integrity checking on a processor-memory bus

Cited by 12 publications

References 5 publications

Protection of heterogeneous architectures on FPGAs: An approach based on hardware firewalls

Protection of heterogeneous architectures on FPGAs: An approach based on hardware firewalls

Memory Encryption for Smart Cards

Preventing integrated circuit piracy using reconfigurable logic barriers

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