A one-micron bipolar VLSI convolver

Abstract

A MAJOR QUESTION IN VLSI is whether the projected improvements in scaling the process technology can be utilized effectively for functions other than memories. Design complexity, pinout limitations, and on-chip interconnect have been suggested as limiting factors in the realization of high throughput processing chips'.The approach to VLSI utilization to be discussed involves the reduction of fundamental algorithms, which are both regular and universal, to regular structures in silicon. The benefits of this emphasis on structural regularity have been demonstrated by other chip designs; multipliers and A-D converters and the microcomputer .A 16-stage digital convolver was selected as the demonstration vehicle for this approach. The resulting design is scalable. Further improvements in process technology will lead to larger and faster convolvers which use the same basic structure and require at most a few more pins.The convolver was designed for an advanced one-micron bipolar technology which was still in final definition. The final process development proceeded in parallel with the detailed chip design. This was done to minimize the usual delay in the exploitation of an advanced process.processing problems, which include radar, sonar, and geophysical processing. The convolver utilizes l p m bipolar technology in performing the convolution function.convolution of x(. ) and C(n) is given by: 2 Convolution and correlation are common t o many signal The mathematical representation for the discrete-time digitalThe convolver has been designed to perform this function directly for N=32 stages, x(n)'s represented by 4b, and c(n))shaving values e, f l , 0. The result is a y(n) represented by 13b in two's complement form at a rate of one result every 3011s.coefficients are serially loaded into a long shift register, and then are dumped in parallel into a set of latches. This approach allows a new set of coefficients to be loaded while the chip is in operation. Note also the pipelined y registers between each adder stage that allows the storage of y(n) partial results on every CLKl pulse.These pipelined registers are immersed directly into the CML gate structure as shown in Figure 2. The logic diagram adjacent to the schematic is an equivalent representation of the generation of the sum bit result. On each CLKl pulse new data is acquired and a sum and carry bit are generated for the next stage.Differential logic was implemented using low voltage current routing techniques. The non-saturating CML gate structures used have 300mV differential output swing and use internal gate source currents as low as 30pA.adder3. It is a two-operand binary adder performing the addition of 2 l l b words from the 16-stage adder array in only 4 CML gate delays, a speed-power-area improvement factor over a standard ripple-carry adder of 3.The computational power of this one chip can be understood by a simple calculation of functional throughput rate. On every cycle of the 30MHz clock, a 32-stage version multiplies a 3b word by a 4b word 32 times i...