A novel zero dead zone PFD and efficient CP for PLL applications

Azadmousavi, Tayebeh; Azadbakht, Mostafa; Aghdam, Esmaeil Najafi; Frounchi, Javad

doi:10.1007/s10470-018-1118-4

Cited by 22 publications

(3 citation statements)

References 20 publications

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“…However, the optimized circuit designed in this paper is only realized by six MOS tubes without the use of unity-gain buffer, which can guarantee the current matching performance and greatly reduce the circuit power consumption and layout area. In the literature [11] , although the unity-gain buffer is not used, a set of switches is added in the feedback loop, which will cause a serious mismatch between the current and the left and right branches of the charge pump, and the problem of switching charge injection will greatly worsen its output ripple. However, the feedback loop designed in this paper does not affect the symmetry of the left and right branches of the charge pump, which has obvious advantages compared with other designs.…”

Section: Figure 3improved Low Loss and Distribution Load Pumpmentioning

confidence: 99%

A design of low mismatch charge pump with feedback compensation current

Nie

Wang³

et al. 2023

2022 2nd Conference on High Performance Computing and Communication Engineering (HPCCE 2022)

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Charge pump is an important module in analog phase -locked loop. The mismatch current greatly affects the in-band noise of CPPLL. To reduce the charge pump mismatch current to improve the overall noise performance of the PLL. In order to reduce the influence of channel length modulation effect on current source, a compensation current is added to the current source of traditional charge pump, and the current is determined by feedback loop. The simulation resultsshow that when the output voltage ranges from 0.4V to 2.8V after the addition of the structure, the charge-discharge mismatch ratio decreases from 7.9% to 0.34%. Thus, the noise performance of the PLL is greatly improved.

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Section: Figure 3improved Low Loss and Distribution Load Pumpmentioning

confidence: 99%

A design of low mismatch charge pump with feedback compensation current

Nie

Wang³

et al. 2023

2022 2nd Conference on High Performance Computing and Communication Engineering (HPCCE 2022)

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“…The dead zone occurs when the PFD is unable to distinguish the phase mismatch of the positive or the negative edges of the two input signals and it may lock to the incorrect phase [33]. The incorrect phase-locked may degrade the phase noise performance.…”

Section: Simulations Of the Pw Calculationsmentioning

confidence: 99%

A Fast Digital Phase Frequency Detector with Preset Word Frequency Searching in ADPLL for a UHF RFID Reader

Ishak

Sampe

Nayan

et al. 2022

Eng. Technol. Appl. Sci. Res.

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An All-Digital Phase-Locked Loop (ADPLL) is an architecture that is widely employed in the communication system due to the advancement of the Complementary Metal-Oxide-Semiconductor (CMOS) technology process. A 2.4GHz Radio Frequency Identification (RFID) system needs a frequency synthesizer in the local oscillator architecture of the transceiver to generate a stable frequency tuning range Therefore, in this paper, a Digital Phase-Frequency Detector (DPFD) is designed to achieve the phase and frequency acquisition in the ADPLL system. The proposed DPFD is divided into two main parts, the first is the Phase Detector (PD) and the second is the Frequency Detector (FD). The PD has managed to detect the presence of the phase difference by recognizing two different input signals. The FD, on the other hand, is capable to detect the higher frequency by identifying the output signals from the PD in digital formation. In addition, a control unit module is developed to control and adjust the Preset Word (PW) for the system by using a binary search scheme. Comparison results show that the final value of the PW from the simulation is the same as from the manual calculation (theoretical values). The digital PFD and the PW control modules are designed and simulated by using Verilog HDL code. These two designed modules will be integrated into the targeted ADPLL to achieve fast locking performance and ultra-low power for Ultra-High Frequency (UHF) RFID applications.

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“…In this case, it is possible to use inhomogeneity of heterostructure and necessary optimization of doping of electronic materials [12] and development of epitaxial technology to improve these materials (including analysis of mismatch induced stress) [13][14][15]. An alternative approaches to increase the dimensions of integrated circuits are using of laser and microwave types of annealing [16][17][18].…”

Section: Introductionmentioning

confidence: 99%

Optimization of Voltage-Controlled Oscillator based on Heterostructure to increase the density of their elements. Influence of Mismatch-Induced Stress and Porosity of Materials on Technological Process Development

Pankratov¹

2022

IJASE

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In this paper we introduced an approach to increase integration rate of field-effect heterotransistors in the framework of a voltage controlled oscillator. We formulate recommendations for optimization of annealing to decrease dimensions of field-effect heterotransistors and to increase their density. At the same time one can decrease transition area between doped and undoped areas of elements of the considered oscillator. Also we consider an approach to decrease the value of mismatch-induced stress in the considered heterostructure. We introduce an analytical approach to model diffusion and ion types of doping with account concurrent changing of parameters in space and time. At the same time the approach gives us possibility to take into account nonlinearity of considered processes.

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A novel zero dead zone PFD and efficient CP for PLL applications

Cited by 22 publications

References 20 publications

A design of low mismatch charge pump with feedback compensation current

A design of low mismatch charge pump with feedback compensation current

A Fast Digital Phase Frequency Detector with Preset Word Frequency Searching in ADPLL for a UHF RFID Reader

Optimization of Voltage-Controlled Oscillator based on Heterostructure to increase the density of their elements. Influence of Mismatch-Induced Stress and Porosity of Materials on Technological Process Development

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