A Novel VLSI Architecture for Image Compression

Paul, Prabal; Girija, P. N.

doi:10.1109/ism.2006.8

Cited by 4 publications

(2 citation statements)

References 8 publications

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“…Many researchers have used a hybrid of two or more transforms in order to compensate for the shortcomings of various transforms; i.e. in image compression [12], image denoising [13], or image coding [14], and watermarking [15]. In this work, a combined approach of the three transforms is used for watermarking: DWT, DCT, and SVD.…”

Section: Watermarking Algorithmsmentioning

confidence: 99%

An Investigation of Watermarking Medical Images

Al-qdah¹,

Alqudah²

2018

Computer Science &Amp; Information Technology

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This paper presents the results of watermarking selected various medical cover images with simple string of letters image (patients' medical data) using a combination of the Discrete Wavelet Transform (DWT) Discrete Cosine Transform (DCT) and singular value decomposition (SVD). The visual quality of the watermarked images (before and after attacks) was analyzed using PSNR and four visual quality metrics (WSNR, MSSIM, PSNR-HVS-M, and PSNR-HVS). The PSNR, PSNR-HVS-M, PSNR-HVS

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Section: Watermarking Algorithmsmentioning

confidence: 99%

An Investigation of Watermarking Medical Images

Al-qdah¹,

Alqudah²

2018

Computer Science &Amp; Information Technology

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“…To benefit from their respective strengths, researchers have developed a new scheme, called hybrid architecture, where multiple transforms are implemented together. For example, the Fourier-wavelet transform can be used to improve the denoising performance for images [7]; a cosine-wavelet hybrid structure can be used to minimize the prediction errors in video coding [4,11] and to enhance the security in digital watermarking [5], etc.…”

Section: Introductionmentioning

confidence: 99%

Hybrid Architecture and VLSI Implementation of the Cosine–Fourier–Haar Transforms

Wahid

Islam

Shimu

et al. 2010

Circuits Syst Signal Process

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This paper presents a VLSI implementation of a novel hybrid architecture that computes three 8-point 1-D transforms-the discrete cosine transform, the discrete Fourier transform, and the Haar wavelet transform-on a single chip. The architecture is developed on matrix factorization and row permutation algorithms, where the basis forward transformation matrices are decomposed into common submatrices which are then shared among the transforms. A two-level hardware mapping has been employed which is parallel, pipelined, and multiplexed. The hybrid architecture, the first of its kind, is implemented using 0.18 µm CMOS technology. The estimated die size of the hybrid processor is 0.203 sq. mm, the frequency of operation is 100 MHz, the gate count is 20,400, and the power consumption is 15.38 mW. Compared to the existing designs, the proposed hybrid scheme has less power density and higher frequency of operation, making it very suitable for modern multimedia-based transcoding applications.

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Hybrid algorithms for spectral noise removal in hyper spectral images

Taha

Loganathan

2020

AIP Conference Proceedings

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A Novel VLSI Architecture for Image Compression

Cited by 4 publications

References 8 publications

An Investigation of Watermarking Medical Images

An Investigation of Watermarking Medical Images

Hybrid Architecture and VLSI Implementation of the Cosine–Fourier–Haar Transforms

Hybrid algorithms for spectral noise removal in hyper spectral images

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