A novel video signal processor with reconfigurable pipelined architecture

Abstract

A programmable 133 MOPS (mega operations per second) processor is designed for video signal processing. It consists of Data-path Processing Part (DPP) and Address Generating Part (AGP). Through a flexible network, the D P P can be efficiently reconfigured as any types of pipelined architecture in terms of video coding algorithms. It is especially suitable to implement irregular algorithms, such as the fast discrete cosine transform (FDCT) and the three-step hierarchical search (3SHS) algorithm for motion estimation. The AGP can generate addresses to perform desired memory access operations for various irregular video coding algorithms. By using this video signal processor (VSP), video processing systems can be easily implemented, and video data can also be smoothly processed in single or multiple VSP configurations. The realization of MPEG-2 is evaluated, and its performance is also presented.