A novel trusted hardware-based scalable security framework for IoT edge devices

Abstract

The Internet of Things (IoT) devices are pervasively deployed and embedded into our daily lives. Over several years, the massive assimilation of IoT devices has given rise to smart cities, smart factories, smart farms, etc. While IoTs can collect immense amounts of user and environmental information, the lack of adequate security measures is among the major concerns about information security and privacy. With the ever-increasing presence of IoTs, information flow between IoT devices in a single or multi-layered network is becoming increasingly vulnerable to attacks. Although several software-based solutions have been developed over the years that improve the security of resource-constrained IoT devices, there are limited efforts on hardware-oriented IoT security solutions. This paper proposes a Trusted HArdware-based Scalable Secure Architecture (THASSA) for IoT Edge systems. Leveraging standard cryptographic algorithms, THASSA provides a secure mechanism for data transfer and off-loads cryptography operations to trusted hardware. The modularized THASSA architecture allows devices to be added or removed without user intervention. Also, THASSA could be scaled to multiple subsystems using multiple trusted hardware to form IoT clusters with secure data path(s) for mission-critical applications. An experimental study has verified the correctness and effectiveness of THASSA.

SHA-256 Hardware Proposal for IoT Devices in the Blockchain Context

“…We present the hardware implementation on an FPGA, highlighting remarkable results regarding the balance between hardware resources, throughput, and power consumption using multiple cores for the SHA-256 algorithm. This proposal is particularly suitable for practical challenges in blockchain environments for IoT devices [ 22 , 23 , 24 ], achieving a throughput of approximately Gbps with 16 cores on a single FPGA and reducing dynamic power consumption by nearly ×1000 compared to existing works. The chosen device for validating the proposal was the Xilinx Virtex 6 xc6vlx240t-1ff1156 FPGA.…”