A Novel Transverse Read Technique for Domain-Wall “Racetrack” Memories

Roxy, Kawsher A.; Ollivier, Sébastien; Hoque, Arifa; Longofono, Stephen; Jones, Alex K.; Bhanja, Sanjukta

doi:10.1109/tnano.2020.3014091

Cited by 15 publications

(7 citation statements)

References 22 publications

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“…In PIRM, these access points are spaced according to the TRD. While TR has been demonstrated for a conservative TRD = 4 [17] our experiments using the LLG magnetic simulator [28] and the resulting resistance levels indicate that TR can be scaled to a TRD = 7 by increasing the sensing current. This yields eight resistance levels which can be encoded by three bits.…”

Section: A Pirm Architecturementioning

confidence: 82%

“…TR was recently proposed [17] and leveraged to improve reliability via detection and correction of over/under-shifting faults [20]. TR is akin to using a portion of a DWM nanowire Fig.…”

Section: Transverse Readmentioning

confidence: 99%

“…To address this concern, and to reduce delay, we propose novel technique Transverse Write (TW) technique with segmented shifting. This is inspired by the shift-based 0 0 0 0 1 1 1 0 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 writing [19] approach and transverse access techniques [17] previously proposed. We illustrate this new concept in Fig.…”

Section: B Poolingmentioning

confidence: 99%

“…Based on the device level information provided in [7], [17], [33], [34], we calculated the timing and energy of read, write and TR operations for DWM. We have designed PIRM's sense circuits for TR and synthesized the PIM logic from Fig.…”

Section: A Comparison With Dwm Pim Techniquementioning

confidence: 99%

“…PIRM achieves multi-operand bulk-bitwise and addition PIM operations that can far outperform current DWM architectures for DRAM, PCM, and DWM. Our approach treats the DWM nanowire as a polymorphic gate using a transverse read [17] (TR), a method to access the nanowire and count the number of ones across multiple domains. Using this ones count we can directly implement Racetracks that are optimized for computing arbitrary logic functions, sum, and carry logic output.…”

Section: Introductionmentioning

confidence: 99%

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PIRM: Processing In Racetrack Memories

Ollivier¹,

Longofono²,

Dutta³

et al. 2021

Preprint

Self Cite

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The growth in data needs of modern applications has created significant challenges for modern systems leading a "memory wall." Spintronic Domain-Wall Memory (DWM), related to Spin-Transfer Torque Memory (STT-MRAM), provides near-SRAM read/write performance, energy savings and nonvolatility, potential for extremely high storage density, and does not have significant endurance limitations. However, DWM's benefits cannot address data access latency and throughput limitations of memory bus bandwidth. We propose PIRM, a DWM-based in-memory computing solution that leverages the properties of DWM nanowires and allows them to serve as polymorphic gates. While normally DWM is accessed by applying spin polarized currents orthogonal to the nanowire at access points to read individual bits, transverse access along the DWM nanowire allows the differentiation of the aggregate resistance of multiple bits in the nanowire, akin to a multilevel cell. PIRM leverages this transverse reading to directly provide bulk-bitwise logic of multiple adjacent operands in the nanowire, simultaneously. Based on this in-memory logic, PIRM provides a technique to conduct multi-operand addition and two operand multiplication using transverse access. PIRM provides a 1.6× speedup compared to the leading DRAM PIM technique for query applications that leverage bulk bitwise operations. Compared to the leading PIM technique for DWM, PIRM improves performance by 6.9×, 2.3× and energy by 5.5×, 3.4× for 8-bit addition and multiplication, respectively. For arithmetic heavy benchmarks, PIRM reduces access latency by 2.1×, while decreasing energy consumption by 25.2× for a reasonable 10% area overhead versus non-PIM DWM.

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Section: A Pirm Architecturementioning

confidence: 82%

“…TR was recently proposed [17] and leveraged to improve reliability via detection and correction of over/under-shifting faults [20]. TR is akin to using a portion of a DWM nanowire Fig.…”

Section: Transverse Readmentioning

confidence: 99%

Section: B Poolingmentioning

confidence: 99%

Section: A Comparison With Dwm Pim Techniquementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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PIRM: Processing In Racetrack Memories

Ollivier¹,

Longofono²,

Dutta³

et al. 2021

Preprint

Self Cite

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Bulk axial Landau levels in the helically magnetized Weyl Hamiltonian and application to multistate memory devices

Rogers,

Chaudhary,

Nguyen

et al. 2024

Phys. Rev. B

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Business Model Selection Model of Distributed Photovoltaic Energy Storage System in China

Wang¹,

Dong²,

Dong³

et al. 2019

2019 IEEE 3rd Conference on Energy Internet and Energy System Integration (EI2)

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It looks very attractive to coordinate racetrack-memory(RM) and stochastic-computing (SC) jointly to build an ultra-low power neuron-architecture. However, the above combination has always been questioned in a fatal weakness that the narrow bit-view of the RM-MTJ structure, a.k.a. shift-and-access pattern, cannot physically match the great throughput of direct-stored stochastic sequences. Fortunately, a recently developed Transverse-Read(TR) provides a wider segment-view to RM via detecting the resistance of domain-walls between a couple of MTJs on single nanowire, therefore RM can be enhanced with a faster access to the sequences without any substantial domain-shift. To utilize TR for a power-efficient SC-DNNs, in this work, we propose a segment-based compression to leverage one-cycle TR to only read those kernel segments of stochastic sequences, meanwhile, remove a large number of redundant segments for ultra-high storage density. In decompression stage,the low-discrepancy stochastic sequences can be quickly reassembled by a select-and-output loop using kernel segments rather than slowly regenerated by costly SNGs. Since TR can provide an ideal in-memory acceleration in one-counting, counter-free SC-MACs are designed and deployed near RMs to form a power-efficient neuron-architecture, in which,the binary results of TR are activated straightforward without sluggish APCs. The results show that under the TR aided RM model, the power efficiency, speed,and stochastic accuracy of Seed-based Fast Stochastic Computing significantly enhance the performance of DNNs. The speed of computation is 2.88× faster in Lenet-5 and 4.40× faster in VGG-19 compared to the CORUSCANT model. The integration of TR with RTM is deployed near the memory to create a power-efficient neuron architecture, eliminating the need for slow Accumulative Parallel Counters (APCs) and improving access speed to stochastic sequences.

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A Novel Transverse Read Technique for Domain-Wall “Racetrack” Memories

Cited by 15 publications

References 22 publications

PIRM: Processing In Racetrack Memories

PIRM: Processing In Racetrack Memories

Bulk axial Landau levels in the helically magnetized Weyl Hamiltonian and application to multistate memory devices

Business Model Selection Model of Distributed Photovoltaic Energy Storage System in China

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