A novel timing-driven placement algorithm using smooth timing analysis

Ayupov, Andrey; Kraginskiy, Leonid

doi:10.1109/ewdts.2008.5580152

Cited by 3 publications

(1 citation statement)

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“…For net-based global placement, Lagrangian relaxation based algorithms, to optimize both performance and total wirelength, were introduced to embed the timing in the problem formulation along with the spreading constraints and showed significant timing improvement compared with commercial wirelength-driven placement flows [17]. A new TDP variation was introduced in [18]; it uses a smooth timing analysis that constructs the timing-cost function as a smooth function of cell placement and uses a net routing algorithm to provide accurate wire delay. While most proposed algorithms focus on late slack optimization, [19] came up with an algorithm to improve the early slack while preserving an optimized late slack by accurately predicting the optimal Steiner tree topologies after each move in the TDP algorithm.…”

Section: Related Workmentioning

confidence: 99%

A Novel Net Weighting Algorithm for Power and Timing-Driven Placement

Chentouf

Ismaili

2018

VLSI Design

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Nowadays, many new low power ASICs applications have emerged. This new market trend made the designer’s task of meeting the timing and routability requirements within the power budget more challenging. One of the major sources of power consumption in modern integrated circuits (ICs) is the Interconnect. In this paper, we present a novel Power and Timing-Driven global Placement (PTDP) algorithm. Its principle is to wrap a commercial timing-driven placer with a nets weighting mechanism to calculate the nets weights based on their timing and power consumption. The new calculated weight is used to drive the placement engine to place the cells connected by the critical power or timing nets close to each other and hence reduce the parasitic capacitances of the interconnects and, by consequence, improve the timing and power consumption of the design. This approach not only improves the design power consumption but facilitates also the routability with only a minor impact on the timing closure of a few designs. The experiments carried on 40 industrial designs of different nodes, sizes, and complexities and demonstrate that the proposed algorithm is able to achieve significant improvements on Quality of Results (QoR) compared with a commercial timing driven placement flow. We effectively reduce the interconnect power by an average of 11.5% that leads to a total power improvement of 5.4%, a timing improvement of 9.4%, 13.7%, and of 3.2% in Worst Negative Slack (WNS), Total Negative Slack (TNS), and total wirelength reduction, respectively.

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Section: Related Workmentioning

confidence: 99%