A Novel Time and Energy Efficient Cubing Circuit Using Vedic Mathematics for Finite Field Arithmetic

Abstract

Cubing plays a vital role in secure communication systems, Signal Processing Applications, Finite Field Arithmetic etc. As the radix of the number used for cubing increases the process gets complicated which in turn increases the delay and power consumption. Vedic mathematics is an ancient mathematics concept that provides a fast and a reliable approach to perform arithmetic operations using sixteen Sutras or word-formulae. In this paper the Anurupya Vedic sutra is used for cubing operations with two different multiplier architectures -One array structured and one tree structure. The performance of these multipliers for cubing applications is compared on the basis of their delay, power consumption and area utilization and it is proved that Anurupya Sutra improves the performance tremendously.