A novel thermal-aware structure of TSV cluster in 3D IC

Hou, Ligang; Fu, Jingyan; Wang, Jinhui; Gong, Na

doi:10.1016/j.mee.2016.03.014

Cited by 11 publications

(3 citation statements)

References 8 publications

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“…Whenever in other study confirmed that the TSV structure can thus reduce the temperature. 9 Table I shows the current-voltage (I-V) for 3D TSV RGB LED chips. The measurements were taken at room temperature using a Keithley 2430 Source Meter with an integrating sphere.…”

Section: Resultsmentioning

confidence: 99%

3D RGB Light Emitting Diodes Prepared by Through Silicon Via Technology

Chang²,

Chen

et al. 2018

ECS J. Solid State Sci. Technol.

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A common cathode 3D RGB light emitting diode chip is produced using through silicon via (TSV) technology. The experimental results show that the diameter, the length and the depth of the Si via are about 140 μm, 50 nm and 320 μm, respectively. The Cu is uniform with a high density in each TSV and the average resistance is about 0.61 mΩ. The measurement of the thermal images shows that the temperature at which a 3D LED (105°C) operates is lower than that for a LED (120°C) when the two devices are injected with a 20 mA current. Using 20 mA current injections, the current-voltage (I-V) output for 3D RGB LED chips is on average 218.84 mW/W, 186.65 mW/W and 324.49 mW/W.

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Section: Resultsmentioning

confidence: 99%

3D RGB Light Emitting Diodes Prepared by Through Silicon Via Technology

Chang²,

Chen

et al. 2018

ECS J. Solid State Sci. Technol.

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“…The TSV structure can thus reduce the temperature of the LED. 18 Figure 7a is actually voltage-current (V-I) characteristics of the 3D LED chips. When the bias voltage was reduced from +3 V to −5 V. The inset of Figure 7a shows the I-V characteristics demonstrate that these devices behave it was found that the reverse current were −7.2 × 10 −9 A at −5 V. With 2.3 × 10 −8 A current injection, we obtained forward voltages of 1.87 V. While for the higher turn-on voltage is that one side of the p-n junction becomes a variable resistor when the opposite side is operating at forward bias.…”

Section: Resultsmentioning

confidence: 99%

Through-Silicon via Submount for Flip-Chip LEDs

Chang

Chen

et al. 2017

ECS J. Solid State Sci. Technol.

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A blue light emitting diode (LED) was prepared by a flip-chip (FC) LED and three-dimensional through-silicon via (3D-TSV) technique. The experimental results indicated that the diameter and length of the Si via were about 180 μm and 400 μm, respectively. The Cu was uniformly and high density filled in each TSV, and the average resistance was about 0.14 m . It was also found that the 96.43Sn-3.57at%Ag bumps were electroplated on the Cu plugged TSVs of a silicon substrate, and these were smoother at 250 • C. After reflow, a 3D blue light emitting diode was prepared by peak bonding at 250 The increasing use of light emitting diodes (LED) in products has promoted the development of higher power, greater density, and lower cost devices. Compared with conventional LED, flip-chip (FC) LED 1-3 have a number of advantages, such as about twice the light output of conventional LED. Flip-chip technology not only shortens the production process, but also significantly reduces thermal resistance and results in a greater heat dissipation rate than seen with the traditional gold wire bonded LED. Moreover, the direct contact of the electrodes or bumps with the package structure can substantially enhance the cooling effect. The flip-chip approach can also remove wire bonding and other wire frame processes, and so these LED can be used with high current drivers.4,5 Therefore, FC LED are attracting growing interest due to their greater heat dissipation, better light emission, higher reliability, and more efficient bonding processes than seen with traditional wire bonded LED.The typical bonding process recommended by chip companies for FC LED is Au/Sn eutectic bonding.6 However, eutectic Sn-Ag alloy is a promising candidate among the various Pb-free solder materials for use with FC LED, and the resulting Sn-Ag alloy bumps 7 can be easily obtained by annealing the Ag/Sn metal stack.There is also demand for new packaging processes for FC LED. 8The use of three-dimensional (3D) packaging through-silicon via (TSV) technology allows a high density of vertical interconnects, unlike 2D packing, as shown in Figure 1. 3D TSV ICs have the following advantages: (1) reduced connection lengths, and thus smaller parasitic capacitance, inductance, and resistance; (2) high-speed low-power interconnects; and (3) a combination of monolithic and multifunctional integration. In this study, a blue LED was prepared using an FC LED and the 3D-TSV technique. We thus propose a new method to achieve 3D LED packing. The detailed fabrication of the TSV and the electrooptical properties of the fabricated are also discussed. ExperimentalFigure 2 presents a schematic diagram of the fabrication process for the 3D LED. A P-type 400 μm thick Si wafer was used as the bottom substrate. Photolithography was used to make a mask for etching the Al layer. A positive type photoresist, AZ-1500, was spin-coated to a thickness of 2 μm with a rotation speed of 500 rpm for 15 s, followed by 3000 rpm for 30 s. The Al layer was etched by wet etching, after using acetone to remove...

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“…Vertical interconnection between upper and lower chips has the advantages of small size, low power consumption, high interconnection density and heterogeneous integration. Similarly, through silicon vias can also reduce their own thermal resistance [ 14 , 15 , 16 ]. It can not only be used as a channel for signals in 3D integrated circuits but also as a channel for heat dissipation in 3D integrated circuits [ 17 ].…”

Section: Introductionmentioning

confidence: 99%

Analysis and Verification of Heat Dissipation Structures Embedded in Substrates in Power Chips Based on Square Frustums Thermal through Silicon Vias

Guo,

Ma,

Ran

et al. 2024

Micromachines

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A novel heat dissipation structure composed of square frustums thermal through silicon via array and embedded in P-type (100) silicon substrate is proposed to improve the heat dissipation capacity of power chips while reducing process difficulty. Based on theoretical analysis, the heat transfer model and thermo-electric coupling reliability model of a power chip with the proposed heat dissipation structure are established. A comparative study of simulation indicates that the proposed heat dissipation structure, which can avoid problems such as softness, poor rigidity, fragility and easy fracture caused by thinning chips has better heat dissipation capability than thinning the substrate of power chips.

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A novel thermal-aware structure of TSV cluster in 3D IC

Cited by 11 publications

References 8 publications

3D RGB Light Emitting Diodes Prepared by Through Silicon Via Technology

3D RGB Light Emitting Diodes Prepared by Through Silicon Via Technology

Through-Silicon via Submount for Flip-Chip LEDs

Analysis and Verification of Heat Dissipation Structures Embedded in Substrates in Power Chips Based on Square Frustums Thermal through Silicon Vias

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