A Novel Structure with Dynamic Operation Mode for Symmetric-Key Block Ciphers

Huang, Kuo-Tsang

doi:10.5121/ijnsa.2013.5102

“…Since message sizes vary, they are usually divided into fixed-size blocks, as required by the symmetric key cipher. Various operating modes have been devised to accommodate various message sizes using symmetric key ciphers, including electronic codebook (ECB) [15], cipher block chaining (CBC) [26], propagating cipher block chaining (PCBC) [24], cipher feedback (CFB) [27], output feedback (OFB) [9], counter (CTR) [22], and Galois counter mode (GCM) [23].…”

Section: Related Workmentioning

confidence: 99%

Patterned Cipher Block for Low-Latency Secure Communication

Oh

¹

,

Park

²

,

Kim

³

2020

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Despite the increasing importance of network security, increasing Internet of Things (IoT) uptake and traffic tends to apply tighter resource constraints for cryptography. To cope with the constraints, security systems must choose between time cost and security. Cyber-attack model evolution and quantum computing technologies have severely limited current cryptography uptake and imposed too much overhead to operate effectively on lightweight communication environments. Therefore, we propose a new operation mode using multiple symmetric key ciphers alternately in a regularized order. The proposed design exploits lightweight cryptography methods, reducing encryption/decryption overhead compared to a single heavy cryptography approach, as well as avoiding exhaustive key extraction attack. Since sequences can change both time cost and security performance widely, the design can be applied to various situations, from the delay-constrained communications to highly secure networks. Our cryptography design incorporates patterned cipher block (PCB) operation, an integrity verification technique to identify if a ciphertext has been forged, handshaking protocol exchanging pattern information and a key using two-round communication, and pattern optimization to maximize the cryptographic performance. We confirmed the proposed operation mode numerically, and verified the outcomes experimentally, confirming that the proposed scheme outperformed current best practice cryptography.

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“…AES encryption is flexible, more secured and fast [14] [20] [16]. It is a popular and secured encryption algorithm in the industry compared to DES [9] [12], but it is prone to side channel attacks.…”

Section: Advanced Encryption Standard (Aes)mentioning

confidence: 99%

Predominance of Blowfish Over Triple Data Encryption Standard Symmetric Key Algorithm for Secure Integrated Circuits Using Verilog Hdl

Swamy¹,

Benakop²

2017

SSRN Journal

1

0

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Computer data communication is the order of the day with Information Communication Technology (ICT) playing major role in everyone's life, communicating with smart phones, tabs, laptops and desktops using internet. Security of the data transferred over the computer networks is most important as for as an organization is concerned. Hackers attempt hard to crack the software key and indulge in cyber crimes. In this paper, the main concern is not only to provide security to the data transferred at the software level but it provides the security at hardware level by the modified Blowfish Encryption and Decryption Algorithms. It results minimum delay, high speed, high throughput] and effective memory utilization compared to Blowfish (BF) and Triple Data Encryption Standard (TDES) algorithms. The implementation of Blowfish with modulo adder and Wave Dynamic Differential Logic (WDDL) is to provide security against Differential power analysis (DPA). In the proposed four implementations, BF with constant delay n-bit adder (BFCDNBA) yielded minimum delay, maximum frequency, high memory utilization and high throughput compared to BF with modulo adder and WDDL logic (BFMAWDDL), BF with modulo adder (BFMA) and TDES algorithms. The VLSI implementation of Blowfish and TDES algorithms is done using Verilog HDL.

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“…After initial permutations, it undergoes 16-rounds of processing steps. It can operate in Cipher Block Chaining (CBC), Electronic Code Book (ECB), Cipher Feedback (CFB) and Output Feedback (OFB) modes [10] [12]. It is prone to Brute Force attack in which hacker attempts to break the key by applying all possible combinations of inputs.…”

Section: Data Encryption Standard (Des)mentioning

confidence: 99%

Predominance of Blowfish Over Triple Data Encryption Standard Symmetric Key Algorithm for Secure Integrated Circuits Using Verilog HDL

Swamy¹,

Benakop²

2017

IJNSA

1

0

View full text Add to dashboard Cite

Computer data communication is the order of the day with Information Communication Technology (ICT) playing major role in everyone's life, communicating with smart phones, tabs, laptops and desktops using internet. Security of the data transferred over the computer networks is most important as for as an organization is concerned. Hackers attempt hard to crack the software key and indulge in cyber crimes. In this paper, the main concern is not only to provide security to the data transferred at the software level but it provides the security at hardware level by the modified Blowfish Encryption and Decryption Algorithms. It results minimum delay, high speed, high throughput] and effective memory utilization compared to Blowfish (BF) and Triple Data Encryption Standard (TDES) algorithms. The implementation of Blowfish with modulo adder and Wave Dynamic Differential Logic (WDDL) is to provide security against Differential power analysis (DPA). In the proposed four implementations

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A Novel Structure with Dynamic Operation Mode for Symmetric-Key Block Ciphers

Abstract: Modern Internet protocols support several modes of operation in encryption tasks

Cited by 15 publications

References 9 publications

Patterned Cipher Block for Low-Latency Secure Communication

Patterned Cipher Block for Low-Latency Secure Communication

Predominance of Blowfish Over Triple Data Encryption Standard Symmetric Key Algorithm for Secure Integrated Circuits Using Verilog Hdl

Predominance of Blowfish Over Triple Data Encryption Standard Symmetric Key Algorithm for Secure Integrated Circuits Using Verilog HDL

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