A Novel Statistical Metrology Framework for Identifying Sources of Variation in Oxide Chemical‐Mechanical Polishing

Abstract

A statistical metrology framework is used to identify systematic and random sources of interlevel dielectric thickness variation. Electrical and physical measurements, technology computer-aided design simulations, design of experiments, signal processing, and statistical analysis are integrated via statistical metrology to deconvolve interlevel dielectric thickness variation into constituent variation sources. In this way, insight into planarization variation is enabled; for a representative chemical/mechanical polishing process, we find that die-level neighborhood interactions are comparable to die level feature dependent effects, and that within each die, die level variation is greater than wafer level variation. The characterization of variation sources via statistical metrology is critical for improved process control, interconnect simulation, and robust circuit design.

Tribological Issues and Modeling of Removal Rate of Low-k Films in CMP

“…25 Many models, some based on fluid dynamics, some on contact mechanics, some physics-based models, chemistry-based models, statistics-based models, and some mathematical models were proposed by several researchers. [26][27][28][29][30][31][32] Most of the models worked on improving Preston's equation, as Preston's equation could not express exactly the effect of consumable properties on the removal rate and could not be used for accurate removal rate prediction. A model proposed recently by Luo and Dornfeld 22 is the subject of investigation in this paper.…”

Wafer Scale Variation of Planarization Length in Chemical Mechanical Polishing

“…Of particular concern is within-die variation in the interlevel dielectric or oxide thickness remaining after polish, due to pattern density variations across the die. 1 Recent modeling of CMP has shown that a "planarization length" parameter, corresponding to the length scale over which raised topography (or pattern density) within a die affects local polishing rate, can be used to predict within-die polish performance. 2 As shown by Stine et al, the planarization length PL is the size of an averaging window used to calculate the "effective density" of raised features on the wafer that the CMP process and pad see during polishing.…”

“…2 As shown by Stine et al, the planarization length PL is the size of an averaging window used to calculate the "effective density" of raised features on the wafer that the CMP process and pad see during polishing. 3 The local oxide removal rate is then [1] where z is the oxide thickness and K is the blanket polish rate. The effective pattern density is a function of location x,y on the die, as calculated using the planarization length PL and chip layout information.…”