A novel simulation methodology for full chip-package thermo-mechanical reliability investigations

Karunamurthy, Balamurugan; Ostermann, Thomas; Bhattacharya, Monojit; Maity, Sandipan

doi:10.1016/j.mejo.2013.12.009

Cited by 4 publications

(2 citation statements)

References 12 publications

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“…The main advantage of multi-scale FEM is the progressive reduction of the computational domain towards the presumed failure region. The multi-scale FEM is based on the cut-boundary method, which assumes that displacement results from the macro-scale model are used to constrain the lower-scale models [15]. Although the multi-scale FEM is widely used in the thermomechanical analysis of power IC, strong limitations can occur because the simulation results are transferred only in one-wayfrom the macro to micro-scale sub-models [13]- [17].…”

Section: Introductionmentioning

confidence: 99%

A Novel Multi-Scale Method for Thermo-Mechanical Simulation of Power Integrated Circuits

Bojita

Purcar

Simon

et al. 2022

IEEE J. Electron Devices Soc.

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During development of power IntegratedCircuits (IC), several iterations between the design and test/ measurement steps are performed. Computer-aided engineering significantly shortens the product development process because the numerical simulations can identify and remediate most deficiencies during the design stage. The recent IC manufacturing technologies lead to ca. 10 4 -order scale separation between transistor cell details and the device active area, resulting in very complex IC models. For the IC complexity to be overcome, advanced multi-scale analysis methods are required to perform accurate simulations in a decent time (order of hours). This paper proposes an advanced and enhanced multi-scale simulation method for the thermo-mechanical analysis of power ICs. The computational IC structure is automatically generated from a Cadence layout and partitioned into far-field and homogenized regions -the macro-model. Detailed localized micro-scale sub-models are assigned to limited portions of the homogenized region. The two-way simulated data transfer between the homogenized macro-model and the micro sub-models is one multi-scale approach novelty proposed in this paper. The method is validated on a real test chip structure presented in literature. The proposed multi-scale approach in conjunction with the two-way macro-micro data transfer lead to similar accuracy in the prediction of defect location, yet with significant simulation time -and computational resource reduction (CPU time and RAM usage reduced by almost 80% and 60% respectively) compared to the method used as reference.

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Section: Introductionmentioning

confidence: 99%

A Novel Multi-Scale Method for Thermo-Mechanical Simulation of Power Integrated Circuits

Bojita

Purcar

Simon

et al. 2022

IEEE J. Electron Devices Soc.

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“…In 2013, the national defense pre research plan bureau (DARPA) released to the industry on a project named "Inner Chip/Chip Enhanced Cooling" (ICECool), which aimed at cooling chip with heat flux density 1KW/cm 2 , heat energy density to 1KW/cm 3 . Undisputedly, the maximum operating temperature of the chip is 413 K, the chip would lost its function because of high temperature gradient if operating temperature was higher [4][5][6]. Therefore, chip cooling had become the bottleneck of further improving the integration.…”

Section: Introductionmentioning

confidence: 99%

Research on Chip Cooling of High Power Density Integrated

Wang¹,

Yang²,

Xi³

2016

Proceedings of the 2016 International Conference on Electrical, Mechanical and Industrial Engineering

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Increasingly, heat flux density on one chip reached to 1KW/cm 2 with the development of integration technology. However, it is hardly to meet the demand of 417K for conventional cooling way. Chip cooling become the bottleneck of integration further. This paper put forward that integrated micro channel in the chip, through which the micro fluid could transfer internal heat to the external. According to the actual working conditions, entrance flow speed and temperature could be adjusted to ensure the normal work of the chip. Firstly, analog chips model including unknown size micro channel was designed. Secondly, the ANYSIS software was adopted to find the proper size. Moreover, size 40μm micro channel could satisfy the high temperature on chip was 413K approximately. Furthermore, the situation of bi-direction flow, changed entrance velocity and entrance temperature was considered to reach the optimized result. It indicated that the chip cooling with micro-channel was feasible. Keywords-micro-channel; integrated chip cooling; the numerical simulation; micro-fluidic I.

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Effect of Die Deflection during Au Wire Bonding Process on Bonding Quality in Overhang Semiconductor Package

Azahar,

Bakar,

Jalar

et al. 2023

J. of Materi Eng and Perform

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A novel simulation methodology for full chip-package thermo-mechanical reliability investigations

Cited by 4 publications

References 12 publications

A Novel Multi-Scale Method for Thermo-Mechanical Simulation of Power Integrated Circuits

A Novel Multi-Scale Method for Thermo-Mechanical Simulation of Power Integrated Circuits

Research on Chip Cooling of High Power Density Integrated

Effect of Die Deflection during Au Wire Bonding Process on Bonding Quality in Overhang Semiconductor Package

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