A Novel Simple CBCM Method Free From Charge Injection-Induced Errors

Chang, YoungChul; Chang, Hung-Wei; Hsieh, Chung-Hsuan; Lai, Hang–Chin; Lu, Tsung-Chien; Ting, W.; Ku, J.; Lu, Chih‐Yuan

doi:10.1109/led.2004.826524

Cited by 25 publications

(7 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The charge-induced error-free charge-based capacitance measurement (CIEF CBCM) [12] in the dashed frame is driven by non-overlapping clock generation circuit to simplify the test procedure. The Figure 4 shows the pulse program.…”

Section: Parasitic Capacitance Test Technique and Structurementioning

confidence: 99%

Accurate SPICE Modeling of Poly-silicon Resistor in 40nm CMOS Technology Process for Analog Circuit Simulation

Sun

Shi

et al. 2015

MATEC Web of Conferences

View full text Add to dashboard Cite

In this paper, the SPICE model of poly resistor is accurately developed based on silicon data. To describe the non-linear R-V trend, the new correlation in temperature and voltage is found in non-silicide poly-silicon resistor. A scalable model is developed on the temperature-dependent characteristics (TDC) and the temperature-dependent voltage characteristics (TDVC) from the R-V data. Besides, the parasitic capacitance between poly and substrate are extracted from real silicon structure in replacing conventional simulation data. The capacitance data are tested through using on-wafer charge-induced-injection error-free charge-based capacitance measurement (CIEF-CBCM) technique which is driven by non-overlapping clock generation circuit. All modeling test structures are designed and fabricated through using 40nm CMOS technology process. The new SPICE model of poly-silicon resistor is more accurate to silicon for analog circuit simulation.

show abstract

Section: Parasitic Capacitance Test Technique and Structurementioning

confidence: 99%

Accurate SPICE Modeling of Poly-silicon Resistor in 40nm CMOS Technology Process for Analog Circuit Simulation

Sun

Shi

et al. 2015

MATEC Web of Conferences

View full text Add to dashboard Cite

show abstract

“…CIEF CBCM [4], shown inside the dashed frame in Fig. 1(a), has been proved to be a precise way for its elimination of the error from charge injection and MOS mismatch.…”

Section: Novel Capacitance Test Techniquementioning

confidence: 99%

Extraction of geometry-related interconnect variation based on parasitic capacitance data

Sun

Cheng

Ren

et al. 2014

IEEE Electron Device Lett.

View full text Add to dashboard Cite

A new interconnect parasitic extraction flow considering geometry-related variation has been proposed in this letter. The 42 interconnect capacitance loads were fabricated by 55-nm process technology and measured to characterize geometric variation. According to the new extraction flow, interconnect technology file (ITF) has been optimized and established. As a result, both extracted error by layout parasitic extraction tool and simulated error by field solver have been improved obviously with this optimized ITF. Meanwhile, an on-chip interconnect test technique with nonoverlapping signal generation circuitry based on charge-induced-injection error-free charge-based capacitance measurement has been designed in this letter to simplify the test procedure.Index Terms-Geometric-related variation, interconnect parasitic extraction, charge-induced-injection error-free charge-based capacitance measurement (CIEF CBCM), non-overlapping signal generation circuitry.

show abstract

“…A total of 8 combinations of channel dimensions for NMOS are used in this study. The capacitance of DUT MOSFET (CDUT) is measured by the charge-injectioninduced-error-free CBCM (CIEF-CBCM) method [6]. The method is based on twice DC current measurements.…”

Section: A Cbcm Test Structurementioning

confidence: 99%

Effective channel length estimation using charge-based capacitance measurement

Tsuji

Terada

2013

2013 IEEE International Conference on Microelectronic Test Structures (ICMTS)

View full text Add to dashboard Cite

An effective channel length is estimated from the capacitance-voltage (C-V) curves of actual size MOSFETs which are measured using charge-based capacitance measurement (CBCM). To evaluate the accurate capacitances between the gate and the channel of sample MOSFETs, their parasitic capacitances are removed by using the test MOSFETs having various channel size and special test structure. A good linear relation between the gate-channel capacitance and the design channel length is obtained and then, the effective channel length is estimated from it. It is found that the obtained effective channel length is shorter than that extracted by the conventional channel resistance method.

show abstract

A Novel Simple CBCM Method Free From Charge Injection-Induced Errors

Cited by 25 publications

References 5 publications

Accurate SPICE Modeling of Poly-silicon Resistor in 40nm CMOS Technology Process for Analog Circuit Simulation

Accurate SPICE Modeling of Poly-silicon Resistor in 40nm CMOS Technology Process for Analog Circuit Simulation

Extraction of geometry-related interconnect variation based on parasitic capacitance data

Effective channel length estimation using charge-based capacitance measurement

Contact Info

Product

Resources

About