A Novel Self-Aligned Double-Channel Polysilicon Thin-Film Transistor

A Low Impact Ionization Rate Poly-Si TFT with a Current and Electric Field Split Design

“…Before evaluating the device's performance, ISE-TCAD was employed to gauge the difference between the conventional device and CES-TFT in the current path, drain electric field, and IIR [13][14][15][16]. The device IIR can be derived by a Chynoweth model and expressed [14] as…”

“…Figure 6 shows the simulated drain side electric field distributions for both structures at V ds = 5 V and V gs = −5 V. The leakage characteristics for both structures can be predicted by a negative gate bias simulation. The lower negative gate bias electric field helps this structure lower the leakage current [13,15]. Figure 7a,b depict the measured transfer curves and device output characteristics for both structures.…”

“…The leakage currents measured at V gs = −6 V and V ds = 5 V for CES-TFT and conventional TFT are found to be 4.13 × 10 −11 A and 1.01 × 10 −8 A, respectively. The threshold voltages (extracted at V ds = 0.1 V) for both devices are 5.4 V (CES-TFT) and 5.2 V (conventional TFT), those values being defined as the V gs at I ds = 10 nA × (channel width (W)/channel length (L)) [13]. It can be observed that the kink effect of the CES device is significantly mitigated because its electron current route circumvents the highest drain electric field region [14].…”

“…A raised source/drain (RSD) structure is an alternative approach to lower device leakage current and drain side electric field effectively, without degrading On-state current seriously [4,12]. However, conventional RSD TFTs, which have thicker source/drain regions with a thin channel, are usually not a self-aligned structure and need an extra mask [13]. Although a self-aligned RSD device can be produced by a damascene process method, it involves more complex fabrication steps, including more chemical mechanical polishing (CMP) processes [12].…”

Design and investigation of N-type metal/insulator/semiconductor/metal structure two-port electro-plasmonic addressed routing switch

“…Contrary to the conventional utilization of SiO 2 as a gate insulator, we attempt to employ HfO 2 to form the multilayer structure [41] as well as today's modern thin-film CMOS technology, such as FinFETs and TFTs [42]. One advantage of this choice as a gate spacer will be to sustain larger thickness of the gate oxide while retaining wanted (good) characteristics of a thin-film SiO 2 of the order of some nanometers or even only some angstroms.…”