A novel reversible two's complement gate (TCG) and its quantum mapping

Chaudhuri, Ayan; Sultana, Mahamuda; Sengupta, Diganta; Chaudhuri, Atal

doi:10.1109/devic.2017.8073946

Cited by 7 publications

(2 citation statements)

References 17 publications

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“…As introduced in [25,26], there are different implementations for 2's complement circuit. To the best of our knowledge, the design in [25] has the minimum quantum cost [11] for 4-bit.…”

Section: B2cmentioning

confidence: 99%

Optimization of Quantum Cost for Low Energy Reversible Signed/Unsigned Multiplier Using Urdhva-Tiryakbhyam Sutra

Elmenyawi¹,

Tawfeek²

2023

Computer Systems Science and Engineering

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One of the elementary operations in computing systems is multiplication. Therefore, high-speed and low-power multipliers design is mandatory for efficient computing systems. In designing low-energy dissipation circuits, reversible logic is more efficient than irreversible logic circuits but at the cost of higher complexity. This paper introduces an efficient signed/unsigned 4 × 4 reversible Vedic multiplier with minimum quantum cost. The Vedic multiplier is considered fast as it generates all partial product and their sum in one step. This paper proposes two reversible Vedic multipliers with optimized quantum cost and garbage output. First, the unsigned Vedic multiplier is designed based on the Urdhava Tiryakbhyam (UT) Sutra. This multiplier consists of bitwise multiplication and adder compressors. Compared with Vedic multipliers in the literature, the proposed design has a quantum cost of 111 with a reduction of 94% compared to the previous design. It has a garbage output of 30 with optimization of the best-compared design. Second, the proposed unsigned multiplier is expanded to allow the multiplication of signed numbers as well as unsigned numbers. Two signed Vedic multipliers are presented with the aim of obtaining more optimization in performance parameters. DesignI has separate binary two's complement (B2C) and MUX circuits, while DesignII combines binary two's complement and MUX circuits in one circuit. DesignI shows the lowest quantum cost, 231, regarding state-ofthe-art. DesignII has a quantum cost of 199, reducing to 86.14% of DesignI. The functionality of the proposed multiplier is simulated and verified using XILINX ISE 14.2.

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“…As introduced in [25,26], there are different implementations for 2's complement circuit. To the best of our knowledge, the design in [25] has the minimum quantum cost [11] for 4-bit.…”

Section: B2cmentioning

confidence: 99%

Optimization of Quantum Cost for Low Energy Reversible Signed/Unsigned Multiplier Using Urdhva-Tiryakbhyam Sutra

Elmenyawi¹,

Tawfeek²

2023

Computer Systems Science and Engineering

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“…Quantum Dot Cellular Automata (QCA) [ [15]. The Boolean XOR gate forms an important parameter in multiple digital circuits, primarily cryptographic circuits.…”

Section: Related Workmentioning

confidence: 99%

Adiabatic Hamming Code Generator-Checker using 4-Dot-2-Electron Quantum Dot Cellular Automata

Chaudhuri,

Sengupta*,

Chudhuri

2019

IJEAT

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Technological advancements have witnessed rapid regression of Moore’s Law within the past few years. With rising demand for higher clocking speeds, CMOS has already started exhibiting threshold limitations. Reversible Logic has emerged as a suitable alternative with near zero heat dissipation attribute. Quantum Dot Cellular Automata (QCA) has adopted the concept of reversibility and emerged as a primitive tool for quantum architecture deigns with clocking near Terra-Hertz range. A plethora of quantum architectures based on QCA cells have been proposed till date. With rise of research on digital designs based on QCA, multiple literary proposals exist which realize digital designs incorporating QCA cells. This communication proposes a Hamming Code Generator-Checker architecture design using 4-dot-2-electron QCA cells. We employ an existing QCA based XOR gate literary proposal for designing the proposed architecture. Peer comparison with literary counterparts has proven our design to fare better with a gain of 60.6% in area.

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