A novel process-controlled-monitor structure suitable for RF CMOS characterization

Chiu, Chia-Sung; Huang, Guo–Wei; Chiu, D.Y.; Chen, K.M.; Cho, M.H.; Wang, S.C.

doi:10.1109/mwsym.2005.1516917

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A Conventional On-wafer and In-line Test Structures1

Introduction1

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2008

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“…As shown in Fig. 1(c), the GSGSG (or GSSG) RF probes can also be utilized to further reduce the length of interconnect [3]. Fig.…”

Section: A Conventional On-wafer and In-line Test Structuresmentioning

confidence: 99%

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Miniature RF Test Structure for On-Wafer Device Testing and In-Line Process Monitoring

Cho

Lee

Peng

et al. 2008

IEEE Trans. Electron Devices

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Abstract-In this brief, a miniature test structure for RF device characterization and process monitoring has been proposed. This new layout design can minimize the voltage drop across interconnects and can prevent capacitive coupling to devices. It consumes only 36% and 40% of the chip area of the conventional on-wafer and in-line test structures, respectively. The RF characteristics of the proposed test structure are shown to be in excellent agreement with those of the conventional ones.

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“…As shown in Fig. 1(c), the GSGSG (or GSSG) RF probes can also be utilized to further reduce the length of interconnect [3]. Fig.…”

Section: A Conventional On-wafer and In-line Test Structuresmentioning

confidence: 99%

“…Although these inline test structures are flexible and suitable for both on-wafer testing and process monitoring, they still consume much chip area and suffer from large IR drop and interconnect parasitics. Recently, an area-efficient RF test structure [3] was presented. As shown in Fig.…”

Section: Introductionmentioning

confidence: 99%