2017
DOI: 10.1016/j.neucom.2017.02.009
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A novel parallel multiplier using spiking neural P systems with dendritic delays

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Cited by 22 publications
(34 citation statements)
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“…In step t + 2 , neurons l (2) i and l (3) i become active after accumulating two spikes. Therefore, according to the maxsequentiality strategy, a randomly selected neuron will be executed.…”
Section: The Universality Of Psn P Systems With Delay Using the Max-sequentiality Strategymentioning
confidence: 99%
See 1 more Smart Citation
“…In step t + 2 , neurons l (2) i and l (3) i become active after accumulating two spikes. Therefore, according to the maxsequentiality strategy, a randomly selected neuron will be executed.…”
Section: The Universality Of Psn P Systems With Delay Using the Max-sequentiality Strategymentioning
confidence: 99%
“…In terms of theoretical research, the computational performance of various extended models is discussed and analyzed, such as: universal or small universal computing systems [6, 14, 21-26, 33-35, 41, 47, 51], language production ability [1,15,46,48,52], design optimization algorithm [50,54], etc. In terms of practical applications [5,49], the SN P system and its variants have also been widely used, such as: pattern recognition [4,36,37], fuzzy SN P systems and fault diagnosis of power systems [31,32,[38][39][40], computational biology [2], solving computational hard problems [12,16,53], performing arithmetic and logical operations, and hardware implementation [3,8,17], etc.…”
Section: Introductionmentioning
confidence: 99%
“…Additionally, simulations of 3-8 decoders on the MeCosim platform were observed and the results infer that the decoders based on the SNPS are efficient. In 2017, a parallel multiplier was constructed using the SNPS with dendritic delays by Díaz, et al [41]. It is important to note that the models discussed above have one common drawback-i.e., the processing of the inputs is sequential, which increases the processing time.…”
Section: Performing Arithmetic and Logical Operations And Hardware Immentioning
confidence: 99%
“…It is important to note that the models discussed above have one common drawback-i.e., the processing of the inputs is sequential, which increases the processing time. The parallel multiplier discussed in [41] can multiply any two natural numbers with long digits in parallel. Moreover, the parallel multiplier has optimized sequential processors which can process multiple units in parallel and then the implementation of the parallel multiplier circuit in FPGA devices, such as spiking neural-network architecture for versatile applications (SNAVA) and field programmable gate array prototypes, also were investigated.…”
Section: Performing Arithmetic and Logical Operations And Hardware Immentioning
confidence: 99%
See 1 more Smart Citation