A novel paradigm of parallel computation and its use to implement simple high-performance hardware

Abstract

Implementing Parallel Algorithms on

<title>Reconfigurable machine for applications in image and video compression</title>

“…The term Xputer stands for a highly efficient non-von Neumann machine paradigm using a data sequencer instead of an instruction sequencer [8]. In contrast to data flow machines, where execution sequences are determined by arbitration, this novel data-procedural paradigm is fully deterministic.…”

The Paramountcy of Reconfigurable Computing

“…We obtain an almost fully symmetric methodology: the only asymmetry is intra-loop parallelism, possible for data streams, however not for instruction streams (Table 11). The semantic difference of these machine paradigms is the state register: the program counter (located with the ALU) for running the instruction streams in executing software, and data counter(s) (located in memory block(s) 327,255 ) for running data streams in executing flowware. Using schematic or flow chart graphical design interfaces, IP blocks, software routines and I/O systems can be quickly combined to explore and develop innovative product functionality without the need for low-level engineering 247 (see section 19.4.2).…”

Hardware/software co-design for data-driven Xputer-based accelerators

“…Xputers are especially designed to reduce the von Neumann bottleneck of repetitive decoding and interpreting address and data computations. High performance improvements have been achieved for the class of regular, scientific computations [3], [10], [11], [12].…”

“…The von Neumann paradigm (used in the FCCM-approach) does not efficiently support "soft" hardware because of its extremely tight coupling between instruction sequencer and ALU: architectures fall apart, as soon as the data path is changed. So a new paradigm is desirable like the one of Xputers, which conveniently supports "soft" ALUs like the rALU concept (reconfigurable ALU) [11] or the rDPA (reconfigurable data path array) [18] [19].…”