A Novel Negative Capacitance Tunnel FET With Improved Subthreshold Swing and Nearly Non-Hysteresis Through Hybrid Modulation

Zhao, Yang; Liang, Zhongxin; Huang, Qianqian; Chen, Cheng; Yang, Mengxuan; Sun, Zixuan; Zhu, Kunkun; Wang, Huimin; Liu, Shuhan; Liu, Tianyi; Peng, Yue; Han, Genquan; Huang, Ru

doi:10.1109/led.2019.2909410

Cited by 32 publications

(12 citation statements)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This behavior could be attributed to the trade-off between the hysteresis characteristic and voltage amplification. [11,20] Namely, the SS will be completely small and the voltage amplification of NC-FET will be improved when the channel length of the device is quite short with sacrifice of hysteresis characteristic.…”

Section: Doi: 101002/adma202005353mentioning

confidence: 99%

“…So far, the majority of NC‐FETs have been demonstrated with silicon‐based channel, in which SS of 30–60 mV dec −1 has been observed. [ 19,20 ] However, silicon‐based MOSFET scaling is quickly approaching the physical limits, specifically 3 nm complementary metal‐oxide–semiconductor (CMOS) production technology will be realized in the next 3–5 years. [ 21 ] Notably, the International Roadmap for Devices and Systems (IRDS) 2020 Edition points out that 2D materials, which preclude short channel effect (SCE), are the most promising candidate to substitute silicon‐based channel to overcome the thermionic and physical channel limit.…”

Section: Figurementioning

confidence: 99%

“…Apart from the V g and V ds , the L ch also mediates the electric characteristics of the 2D MoS 2 NC‐FET. [ 20,31,34 ] We fabricated multiple channels on the bilayer MoS 2 nanoflakes with L ch of 0.77, 1.50, 2.31, and 3.28 µm, as shown in Figure a. The transfer curves of the as‐fabricated NC‐FET with different L ch at V g step and V ds of 5 mV and 0.1 V, respectively, are summarized in Figure 3b and Figure S8 in the Supporting Information.…”

Section: Figurementioning

confidence: 99%

See 2 more Smart Citations

Record‐Low Subthreshold‐Swing Negative‐Capacitance 2D Field‐Effect Transistors

et al. 2020

View full text Add to dashboard Cite

Power consumption is one of the most challenging bottlenecks for complementary metal‐oxide–semiconductor integration. Negative‐capacitance field‐effect transistors (NC‐FETs) offer a promising platform to break the thermionic limit defined by the Boltzmann tyranny and architect energy‐efficient devices. However, it is a great challenge to achieving ultralow‐subthreshold‐swing (SS) (10 mV dec−1) and small‐hysteresis NC‐FETs simultaneously at room temperature, which has only been reported using the hafnium zirconium oxide system. Here, based on a ferroelectric LiNbO3 thin film with great spontaneous polarization, an ultralow‐SS NC‐FET with small hysteresis is designed. The LiNbO3 NC‐FET platform exhibits a record‐low SS of 4.97 mV dec−1 with great repeatability due to the superior capacitance matching characteristic as evidenced by the negative differential resistance phenomenon. By modulating the structure and operating parameters (such as channel length (Lch), drain–sourse bias (Vds), and gate bias (Vg)) of devices, an optimized SS from ≈40 to ≈10 mV dec−1 and hysteresis from ≈900 to ≈60 mV are achieved simultaneously. The results provide a new potential method for future highly integrated electronic and optical integrated energy‐efficient devices.

show abstract

Section: Doi: 101002/adma202005353mentioning

confidence: 99%

Section: Figurementioning

confidence: 99%

Section: Figurementioning

confidence: 99%

See 1 more Smart Citation

Record‐Low Subthreshold‐Swing Negative‐Capacitance 2D Field‐Effect Transistors

et al. 2020

View full text Add to dashboard Cite

show abstract

“…At the point when an outer potential is applied across a FE material, the dipole moment causes polarization, thereby leading to tunable NC. Hence, any FE material above oxide layer in a FET counteracts effective gate capacitance because of capacitance matching which prompts voltage intensification [26]. This gives impressive improvement in I ON , I OFF and SS in NC-MOSFET.…”

Section: Introductionmentioning

confidence: 99%

Ge/GaAs Based Negative Capacitance Tunnel FET Biosensor: Proposal and Sensitivity Analysis

Paul

Rajan

Samajdar

et al. 2022

Silicon

View full text Add to dashboard Cite

A highly sensitive, accurate, fast and power efficient biosensor is the need of the hour. Undoubtedly, dielectrically modulated (DM) tunnel FET (TFET) assures better sensitivity as compared to MOSFET biosensors in case of label-free biosensing. However, there exists immense possibilities to upgrade TFET biosensor properties through the improvement of its DC characteristics. Therefore, in this paper a ferroelectric (FE) gate oxide and a hetero material (HM) source/drain-channel based TFET is designed for biosensor applications. A FE layer of HfZrO 2 above SiO 2 gives rise to negative capacitance (NC) effect that causes voltage amplification and hence, boosts subthreshold swing (SS) and I ON /I OFF ratio. In addition, use of a low band gap material (Ge) in source and a high band gap material (GaAs) in drain-channel junctions enhances the probability of band-to-band-tunneling (BTBT) of charge carriers. Further, to introduce biomolecules, a cavity is impinged below HfZrO 2 near SiO 2 above source/channel junction that modulates BTBT as a function of charge density (N f ) and dielectric constant (K). This paper presents a detailed comparative analysis of Ge/GaAs-NCTFET and Ge/GaAs-TFET biosensors for different K and N f values from which we can conclude that the incorporation of NC effect in TFET biosensors leads to enhanced sensitivity with high speed and low power consumption.

show abstract

“…On that account, the development of device technologies is necessary to get the final objective of real and big-scale IoT applications [1][2]. The low power specially low stand-by power is the most essential requirement for devices in IoT application [3].…”

Section: Introductionmentioning

confidence: 99%

Design of HeterojunctionTunnel Field-Effect Transistors with SiO2 isolation between Source and Drain for Low Power Application

Chander

Sinha

Singh

et al. 2021

Preprint

View full text Add to dashboard Cite

This paper presents a numerically simulated Ge-source based Tunnel Field Effect Transistor with (TFETs) SiO 2 segregation between the channel and drain. The developed device has been compared with conventional TFET and without isolated heterojunction TFET. The use of oxide segregation between channel and drain enhances the performance of the device in terms of ON-state current as well as subthreshold swing (SS). The electrical characteristics such as surface potential, electric field, transfer characteristics, output characteristics of the proposed device have been studied. The temperature variation of the proposed device has also been studied. The proposed device offers high ON current of 3x10 4 A, I ON /I OFF ratio of ~10 11, and enhanced SS of 30 mV/dec. The validity of the proposed device has been done by Synopsys Sentaurus TCAD.

show abstract

A Novel Negative Capacitance Tunnel FET With Improved Subthreshold Swing and Nearly Non-Hysteresis Through Hybrid Modulation

Cited by 32 publications

References 10 publications

Record‐Low Subthreshold‐Swing Negative‐Capacitance 2D Field‐Effect Transistors

Record‐Low Subthreshold‐Swing Negative‐Capacitance 2D Field‐Effect Transistors

Ge/GaAs Based Negative Capacitance Tunnel FET Biosensor: Proposal and Sensitivity Analysis

Design of HeterojunctionTunnel Field-Effect Transistors with SiO2 isolation between Source and Drain for Low Power Application

Contact Info

Product

Resources

About