A Novel Multilevel Inverter With Self-Balancing Capability of Capacitors Voltage; Structure, Modulation, and Operation

Pourfarrokh, Shayan; Adabi, Jafar; Zare, Firuz

doi:10.1109/jestpe.2022.3222344

Cited by 13 publications

(8 citation statements)

References 38 publications

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“…The superiority of the proposed 17-level asymmetrical fault tolerant MLI architecture is demonstrated by comparing with the reported similar MLI topologies 24,25,[28][29][30][31][32] and FT topologies published in previous studies [6][7][8][9]11,[33][34][35] as shown in Tables 4 and 5, respectively. Table 4 shows that the proposed topology required a lower number of DC sources in comparison to previous works 24,25,[29][30][31][32] and the same number of capacitors and dc-sources as Pourfarrokh et al 28 Further, the topologies 24,25,[29][30][31][32] have the higher TBV value as compare to the proposed topology. On the other hand, the MLI topologies proposed in previous studies 24,25,[29][30][31][32] fail to tolerate fault on switch(es).…”

Section: Comparative Analysismentioning

confidence: 70%

“…A new 17-level cascaded MLI topology is developed with four sources in Siddique et al 31 Asymmetrical MLI with low switching frequency is developed with four dc sources in Siddique et al 32 Further, the other limitation of the topologies reported in Dhanamjayulu et al, 29 Shunmugham Vanaja and Stonier, 30 and Siddique et al 31,32 is that they have higher blocking voltage than the proposed topology. The above-mentioned topologies [22][23][24][25][26][27][28][29][30][31][32] produce a higher number of voltage levels with an asymmetrical source configuration, but the failure of switching devices causes the system to malfunction or shut down completely. In Aly et al, 33 a five-level FT-MLI topology is developed to tolerate the both OC and SC switch faults.…”

Section: Introductionmentioning

confidence: 99%

“…In Das et al, 27 a 13‐level MLI is developed with four sources. A novel 17‐level MLI topology is developed with self‐capacitor voltage balancing in Pourfarrokh et al 28 However, the total blocking voltage (TBV) is high as compared to the proposed topology. In Dhanamjayulu et al, 29 a hybrid CHB MLI is developed to produce 17‐level voltage with 4 dc‐sources, 4 capacitors, and 16 switches.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Highly resilient 17‐level fault‐tolerant multilevel inverter topology with reduced capacitor size

Chappa,

Gupta,

Sahu

et al. 2023

Circuit Theory & Apps

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SummaryMultilevel inverters (MLIs) have recently drawn the huge attention of industry and academia since they are becoming a viable technology for a variety of applications. However, the risk of failure of the converter increases with the increasing number of component count for applications involving heavy duty and continuous operation. In this context, an asymmetrical source configured FT‐MLI (fault tolerant‐MLI) topology is investigated and developed with less number of device count and having the ability to withstand both OC (open‐circuit) and SC (short‐circuit) switch faults on single and multiple switches. The proposed architecture maintains the same output voltage levels and power in both pre‐ and post‐fault operations. In addition, a switching method is developed to reduce the capacitors' size by minimizing the voltage ripple. Furthermore, without the need for an external circuit, the voltage across the capacitors remains balanced in both pre‐ and post‐fault operations. The simulation and experimental results are provided to demonstrate the effectiveness of the proposed asymmetrical FT‐MLI topology. Finally, a comparison of the proposed topology with the existing MLI topologies is shown to emphasize the benefits of the proposed system.

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Section: Comparative Analysismentioning

confidence: 70%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Highly resilient 17‐level fault‐tolerant multilevel inverter topology with reduced capacitor size

Chappa,

Gupta,

Sahu

et al. 2023

Circuit Theory & Apps

View full text Add to dashboard Cite

show abstract

“…A secondary strategy for canceling harmonics is active harmonic compensation, which involves injecting extra currents into the power supply proactively. Often, these strategies require extra hardware and intricate control algorithms, which can be implemented with digital signal processors or harmonic controllers [4,5].…”

Section: Introductionmentioning

confidence: 99%

Kalman Filter-Based Harmonic Distortion Mitigation Technique for Microgrid Applications

Iqbal,

Khalid,

Riggs

et al. 2024

Applications and Optimizations of Kalman Filter and Their Variants

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This work presents a Kalman filter-based harmonic mitigation technique that can be used to reduce the total harmonic distortion (THD) of grid-injected current by reducing the harmonic distortion. Throughout the power supply system, power electronic converters have become increasingly used in recent years, which has resulted in more reactive power and harmonics. In a power system, harmonics add to noise and lower power quality. A study in MATLAB/Simulink 2022b for improving the THD of renewable energy injected grid currents using seven-level packed u-cells (PUC7) has been undertaken to improve the grid-injected current THD with Kalman filter-based harmonic mitigation technique. With the Kalman filter-based harmonic mitigation techniques, the THD for the grid-injected current is improved from 6.32 to 2.49% when compared to the grid-injected current without the Kalman filter-based technique.

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“…In [17], Ye proposed a 13-level inverter with a reduced switch count and high boosting ability, and he further improved the topology in [18]. The 17-level SC inverters are proposed in [19][20][21], all of which show their pros and cons, respectively. The topologies presented in [19,20] both have the advantage of a low component count, but the capacitor voltage in [19] cannot balance inherently and [20] employs more than one DC source.…”

Section: Introductionmentioning

confidence: 99%

A Switched Capacitor Inverter Structure with Hybrid Modulation Method Lowering Switching Loss

Zhao

Liang

et al. 2023

Energies

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The high-frequency modulation method (HFM) for a switched capacitor (SC) inverter often leads to high switching loss since it increases switching frequency. In order to reduce the switching frequency and switching loss in the HFM for SC inverter, this paper proposes a novel hybrid modulation strategy as well as a corresponding demo switched capacitor topology. The hybrid strategy limits the number of high-frequency switches, thus reducing the switching loss significantly. Meanwhile, the demo topology maintains the merits of current switched capacitor inverter such as low switch count, quadruple voltage-boosting ability and self-balancing capacity. The principle of the hybrid modulation method and the circuit configuration of the inverter are analyzed in detail. And comparisons are introduced to demonstrate the advantages of the proposed modulation method and topology. Finally, experimental results have proved the feasibility of the proposed inverter.

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A Novel Multilevel Inverter With Self-Balancing Capability of Capacitors Voltage; Structure, Modulation, and Operation

Cited by 13 publications

References 38 publications

Highly resilient 17‐level fault‐tolerant multilevel inverter topology with reduced capacitor size

Highly resilient 17‐level fault‐tolerant multilevel inverter topology with reduced capacitor size

Kalman Filter-Based Harmonic Distortion Mitigation Technique for Microgrid Applications

A Switched Capacitor Inverter Structure with Hybrid Modulation Method Lowering Switching Loss

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