A Novel Multifin Dynamic Random Access Memory Periphery Transistor Technology Using a Spacer Patterning through Gate Polycrystalline Silicon Technique

Abstract

A new technique that integrates the metal gate multifin field effect transistor (multi-FinFET) and the conventional polycrystalline silicon (poly-Si) gate planar FET is proposed. It solves the problems of the previous scheme, such as the complicated process integration due to the coexistence of TiN gate FinFETs and poly-Si gate planar FETs, the fin width consumption by multiple gate oxidation, the large fin pitch limited by the resolution of lithography, and the gap-filling ability of shallow trench isolation (STI). The newly proposed technique forms multifin structures by spacer patterning through the gate poly-Si electrode for planar FETs. The drain current gain due to an increase in effective channel width is estimated, and the basic electrical characteristics of a multi-FinFET are evaluated.

Recent Progress in Simple and Cost‐Effective Top‐Down Lithography for ≈10 nm Scale Nanopatterns: From Edge Lithography to Secondary Sputtering Lithography

“…[113,114] In the early stage, it was referred to as spacer technology and was used primarily for making gates of fine field effect transistors (FETs) smaller with spacers. [78,79,100,106,[115][116][117][118] Later, in the late 2000s, as EUV lithography was used in the semiconductor industry instead of spacer lithography for sub 10 nm sizes, spacer lithography was used in other electronic-based devices such as gas and biosensors, [102,119] which required high-resolution and high-aspectratio structures. In the 2010s, it began to expand not only to electronic devices, but also to a variety of applications [27] such as nanowire fabrication, [120] nanogenerators, [121] and omniphobic surfaces.…”