A novel multichannel UART design with FPGA-based implementation

Thai, Ngoc Pham; Ngoc, Bao Ho; Duy, Tan Do; Truong, Phuc Quang; Phan, Van Ca

doi:10.1504/ijcat.2021.122350

Cited by 5 publications

(3 citation statements)

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“…Circuit topology is used to determine how to partition the scan chain, which im-proves the number of scan segments that can be skipped. According to the results of the simulation, the suggested approach lowers the test power usage [4].…”

Section: Literature Surveymentioning

confidence: 99%

Design and Implementation of Verilog Based High Speed Low Power UART

Ms. Banti Kumari,

Ms. Kanika Jindal,

Mr. Amit Bindal

2024

Int Res J Adv Engg Hub

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The most crucial component of serial communication is a microcircuit called a universal asynchronous receiver/transmitter (UART). Receive-transmitter asynchronous technology is known as UART, and it is widely used for device-to-device communication protocols. Using asynchronous serial communication at a speed that can be adjusted. A hardware communication technique called UART Asynchronous conditions occur when the output of the transmitting device and the receiving end are not in sync with a clock. In UART, receiving a signal is known as RxD, and transmitting a signal is known as TxD. In comparison to the existing conventional UART design, we were able to reduce delay by 29% and power usage by 33% using our approach. The effectiveness of the novel UART design is noticed with the reduction in delay and power consumption. Synthesis and simulation are done in Xilinx ISE and Modelsim and Verilog HDL is used to implement a unique UART design.

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Section: Literature Surveymentioning

confidence: 99%

Design and Implementation of Verilog Based High Speed Low Power UART

Ms. Banti Kumari,

Ms. Kanika Jindal,

Mr. Amit Bindal

2024

Int Res J Adv Engg Hub

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“…The sender rs232_tx sends serial data in r_data according to the count of bit_cnt. When bit_cnt counts to 10 and bit_flag is high level, a done signal is generated, making the state set to low level to end the transmission [9] 4'd4:rs232_tx <= r_data [3]; 4'd5:rs232_tx <= r_data [4]; 4'd6:rs232_tx <= r_data [5]; 4'd7:rs232_tx <= r_data [6]; 4'd8:rs232_tx <= r_data [7]; 4'd9:rs232_tx <= 1'b1; default:rs232_tx <= 1'b1; endcase end end else rs232_tx <= 1'b1; end When the send flag bit_flag is high, the bit counter bit_cnt starts countingWhen bit_cnt is 0, rs232_tx sends out starting bit (low level). When bit_cnt ranges from 1 to 8, rs232_tx sends eight bits of r_data from low to high.…”

Section: Uart Sending Modulementioning

confidence: 99%

Design And Implementation of UART Based on Verilog HDL

Kong¹,

Niu²,

Yang³

2023

HSET

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As a two-way transmission channel, Universal Asynchronous Receiver/Transmitter (UART) not only greatly improves the efficiency of information transmission between computers and external devices, but also ensures the accuracy and consistency of information by eliminating metastable state, setting baud rate and other means. In this paper, on the basis of fully understanding the definition and function of UART, based on Verilog HDL language to build UART, and through Modelsim simulation, image and data. The experimental results show that the receiving and sending module of this module works well and meets the requirements of full-duplex serial communication equipment. There is no doubt that the design of this paper has made a more detailed explanation of the basic operating principle of UART, which will contribute to its further development.

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“…It can be reprogrammed to implement various logic functions that ASICs do not have [2]. Additionally, FPGA can be tested using the development board, dwindling the time and cost of design, so the project is based on FPGA [3].…”

Section: Introductionmentioning

confidence: 99%

Design, refinement, and enhancement of FPGA-implemented UART circuitry

2024

ACE

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This article provides an overview of the universal asynchronous receiver/transmitter, commonly referred to as Universal Asynchronous Receiver/Transmitter (UART). The UART stands as a noteworthy exemplar of a serial communication protocol, facilitating the exchange of data within a serial connection while accommodating full-duplex communication. The architecture of the UART hinges upon three principal constituents: the transmitter, the receiver, and the baud rate generator, the latter essentially a frequency divider. Each of these elements is meticulously crafted using the Verilog hardware description language, thereby ensuring distinct and efficient design. Furthermore, this discourse delves into refined iterations of these implementations. For instance, it introduces the concept of a baud rate self-adaptive function and expounds upon multibyte transmission techniques. In a concerted effort to streamline circuit design and curtail the electro circuit's footprint, a deliberate decision is made to forgo the integration of a parity check module. Consequently, the chosen data format is the widely adopted 8N1 (8 data bits, 1 stop bit and no parity bit) configuration.

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A novel multichannel UART design with FPGA-based implementation

Cited by 5 publications

References 0 publications

Design and Implementation of Verilog Based High Speed Low Power UART

Design and Implementation of Verilog Based High Speed Low Power UART

Design And Implementation of UART Based on Verilog HDL

Design, refinement, and enhancement of FPGA-implemented UART circuitry

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