A Novel Multi-Core Approach for Functional Safety Compliance of Automotive Electronic Control Unit According to ISO 26262

Nag, Pramit; Ghanekar, Umesh; Harmalkar, Jyoti

doi:10.1109/i2ct45611.2019.9033841

Cited by 4 publications

(1 citation statement)

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“…Meantime, the state-ofthe-art ADAS functionalities are usually Quality Management (QM) and subject to the driver control and responsibility. Wherefore, autonomous driving transfers this responsibility to complex ADAS multicore critical systems depending on the autonomy level that results in producing highly safety-critical functions with high-performance requirements, as they have been introduced in the literature [8, 13,14]. Moreover, traditional safety-critical mechanical features, such as antilock braking, have moved towards new autonomous driving solutions, such as the electronic stability program with the help of networked layered architecture systems.…”

Section: Figure 1 Multicore Architecture Block Diagrammentioning

confidence: 99%

ISO-26262 Compliant Safety-Critical Autonomous Driving Applications: Real-Time Interference-Aware Multicore Architectures

El-Bayoumi¹

2021

IJSSE

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Over the decades, autonomous vehicles have been developed and qualified using variant single-core architectures. With the evolutionary trend of safety critical applications, innovative safety design methodologies have raised present requirements constraints and limitations to mitigate such design complexity deviations. The main objectives of this work are to investigate, evaluate and introduce an efficient safety-critical multi-cache multicore architecture, that is fully compliant with methods and principles of ISO 26262. Moreover, this paper presents new safety design choices applied to timing monitoring, temporal protection, runtime monitoring and services protection to overcome multicore processor challenges in runtime that eventually decay the worst case execution time and the interconnections (symmetric and asymmetric processors, critical timing, data coherency and synchronization predictability, core interconnects, etc.), as well as to tolerate real-time interference faults.

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Section: Figure 1 Multicore Architecture Block Diagrammentioning

confidence: 99%