A novel MNOS technology using gate hole injection in erase operation for embedded nonvolatile memory applications

Ito, Fuminori; Kawashima, Yasunaru; Sakai, Takeshi; Kanamaru, Y.; Ishii, Yuichiro; Mizuno, Masayuki; Hashimoto, Takahiro; Ishimaru, T.; Mine, T.; Matsuzaki, N.; Kume, Haruki; Takano, Teruo; Shinagawa, Y.; Toya, Tomoyuki; Okuyama, K.; Kuroda, K.; Kubota, K.

doi:10.1109/vlsit.2004.1345404

Cited by 5 publications

(1 citation statement)

References 2 publications

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“…Recently, there have been several reports on EEPROM cells with various types [4]- [7]. Also, our group reported an EEPROM cell using a self-aligned select gate which surrounds the floating gate [8].…”

Section: Introductionmentioning

confidence: 99%

Fabrication and characterization of a new EEPROM cell with spacer select transistor

Lee

Jeong

et al. 2005

IEEE Electron Device Lett.

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In this letter, process technology and cell characteristics of a newly developed compact electrically erasable programmable read only memory cell are described. The cell has spacer select gates on both side walls of floating gate and this gives a very small cell size as well as relief of topology during contact formation. The cell size is 0.95 m 2 with 0.18 m logic process. The cells are programmed and erased by Fowler-Nordheim tunneling. It appears that programming requires 3 ms at 16 V while erasing requires 2 ms at 14 V. It is shown that the cells have very uniform distribution of both programmed and erased threshold voltage. It is also shown that the cell endures up to half million cycling tests. Index Terms-Electrically erasable programmable read only memory (EEPROM) cell, embedded electrically erasable programmable read only memory (EEPROM), endurance, Floating-gate, Fowler-Nordheim (FN) tunneling, select gate.

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Section: Introductionmentioning

confidence: 99%