A novel method for source/drain ion implantation for 20 nm FinFETs and beyond

Qin, Changliang; Yin, Huaxiang; Wang, Guilei; Zhang, Yanbo; Liu, Jinbiao; Zhang, Qingzhu; Zhu, Huilong; Zhao, Chao; Radamson, Henry H.

doi:10.1007/s10854-019-01274-4

Cited by 3 publications

(3 citation statements)

References 18 publications

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“…5 Finally, this technique is incompatible with 3D nanostructured materials since it does not provide conformal dopant incorporation for non-planar nanostructures. 6 Plasma immersion ion implantation, also referred to as plasma doping, is an emerging technique based on the extraction of accelerated ions from a plasma by applying a high voltage in order to implant them in a semiconductor substrate. 7 This technique offers significant advantages over conventional ion implantation, since the doping profiles are generally more conformal than those obtained using conventional ion implantation.…”

Section: Introductionmentioning

confidence: 99%

“…This selflimiting reaction has been used in combination with conventional spike annealing to enable the formation of B, P and As sub-5 nm ultra-shallow junctions in Si. 6,[9][10][11] Nanoscale doping of InAs, 12,13 In x GA y As z , 14,15 InP, 16 Ge [17][18][19] and SiGe 20 via monolayers of dopant containing molecules has been demonstrated as well. This gentle approach, usually referred to as monolayer doping (MLD), has been proven to be efficient in introducing controlled amounts of dopants in Si nanowires 9 and InP nanopillars.…”

Section: Introductionmentioning

confidence: 99%

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Doping of silicon by phosphorus end-terminated polymers: drive-in and activation of dopants

et al. 2020

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Doping of silicon by phosphorus end-terminated polymers: drive-in and activation of dopants

et al. 2020

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“…Except for the requirement of conformality, parasitic resistance is another challenge that needs to be addressed. As the critical dimension of devices decreases, the contact area decreases accordingly, and it is necessary to achieve a higher dopant activation level in S/D to lower the contact resistivity [214,[219][220][221][222][223]. At present, the S/D of PMOS are p-type doped SiGe epitaxial films where the doping procedure is accomplished by boron in situ doping or implantation.…”

Section: Solid-state Diffusionmentioning

confidence: 99%

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

Radamson,

Miao,

Zhou

et al. 2024

Nanomaterials

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After more than five decades, Moore’s Law for transistors is approaching the end of the international technology roadmap of semiconductors (ITRS). The fate of complementary metal oxide semiconductor (CMOS) architecture has become increasingly unknown. In this era, 3D transistors in the form of gate-all-around (GAA) transistors are being considered as an excellent solution to scaling down beyond the 5 nm technology node, which solves the difficulties of carrier transport in the channel region which are mainly rooted in short channel effects (SCEs). In parallel to Moore, during the last two decades, transistors with a fully depleted SOI (FDSOI) design have also been processed for low-power electronics. Among all the possible designs, there are also tunneling field-effect transistors (TFETs), which offer very low power consumption and decent electrical characteristics. This review article presents new transistor designs, along with the integration of electronics and photonics, simulation methods, and continuation of CMOS process technology to the 5 nm technology node and beyond. The content highlights the innovative methods, challenges, and difficulties in device processing and design, as well as how to apply suitable metrology techniques as a tool to find out the imperfections and lattice distortions, strain status, and composition in the device structures.

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An 8-nm-thick Sn-doped polycrystalline β -Ga2O3 MOSFET with a “normally off” operation

Yoon

Kim

Cho

et al. 2021

Applied Physics Letters

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Monoclinic gallium oxide (β-Ga2O3) has attracted the interest of the scientific community due to its application in power electronics. Power electronics that need to handle a high voltage often uses a “normally off” device with a positive threshold voltage due to its fail-safe operation and its simple system architecture. In this work, 8-nm-thick Sn-doped polycrystalline β-Ga2O3 thin films were investigated as a channel material for power electronics, and their properties were characterized. The optical bandgap of the 8-nm-thick Sn-doped β-Ga2O3 was determined to be 5.77 eV, which is larger than that of 100-nm-thick Sn-doped β-Ga2O3 due to the quantum confinement effect. The developed back-gated device demonstrated normally off behavior and exhibited a voltage handling capacity as high as 224 V (2.88 MV/cm). This ultrathin β-Ga2O3 layer could also be applied to fields other than power electronics, including displays, optical sensors, photocatalytic sensors, and solar cells.

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A novel method for source/drain ion implantation for 20 nm FinFETs and beyond

Cited by 3 publications

References 18 publications

Doping of silicon by phosphorus end-terminated polymers: drive-in and activation of dopants

Doping of silicon by phosphorus end-terminated polymers: drive-in and activation of dopants

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

An 8-nm-thick Sn-doped polycrystalline β -Ga2O3 MOSFET with a “normally off” operation

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