A Novel Metal Scheme and Bump Array Design Configuration to Enhance Advanced Si Packages CPI Reliability Performance by Using Finite Element Modeling Technique

Chang, Kuo-Chin; Lii, Mirng-Ji; Hsu, Steven; Hao-chun, Liu; Lai, Yen-Kun; Tsai, Sheng-Han; Hsu, Chieh-Hao

doi:10.1109/ectc.2019.00067

Cited by 4 publications

(2 citation statements)

References 15 publications

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“…Therefore, the stress recovery peak should be attributed to the superposition of two stresses generated by the chip-solder layer CTE mismatch and the solder layer and copper layer CTE mismatch. In addition, probably due to this stress superposition effect, the maximum σ N reached 41.1 MPa under the non-fixed constraint [33].…”

Section: Effects Of Modeling Scopementioning

confidence: 95%

“…This was evidenced by the fact that the maximum σ Q value in model III (Figure 7B) was lower than the maximum σ N value in model II (Figure 5B). This complex interaction also affected the magnitude of stress recovery peak in model III [33]. To further analyze the effect of different substrate types or specifications on the stress recovery peak, the model II was used for σ N simulations.…”

Section: Effects Of Substratesmentioning

confidence: 99%

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Study of Thermal Stress Fluctuations at the Die-Attach Solder Interface Using the Finite Element Method

et al. 2021

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Solder joints in electronic packages are frequently exposed to thermal cycling in both real-life applications and accelerated thermal cycling tests. Cyclic temperature leads the solder joints to be subjected to cyclic mechanical loading and often accelerates the cracking failure of the solder joints. The cause of stress generated in thermal cycling is usually attributed to the coefficients of thermal expansion (CTE) mismatch of the assembly materials. In a die-attach structure consisting of multiple layers of materials, the effect of their CTE mismatch on the thermal stress at a critical location can be very complex. In this study, we investigated the influence of different materials in a die-attach structure on the stress at the chip–solder interface with the finite element method. The die-attach structure included a SiC chip, a SAC solder layer and a DBC substrate. Three models covering different modeling scopes (i.e., model I, chip–solder layer; model II, chip–solder layer and copper layer; and model III, chip–solder layer and DBC substrate) were developed. The 25–150 °C cyclic temperature loading was applied to the die-attach structure, and the change of stress at the chip–solder interface was calculated. The results of model I showed that the chip–solder CTE mismatch, as the only stress source, led to a periodic and monotonic stress change in the temperature cycling. Compared to the stress curve of model I, an extra stress recovery peak appeared in both model II and model III during the ramp-up of temperature. It was demonstrated that the CTE mismatch between the solder and copper layer (or DBC substrate) not only affected the maximum stress at the chip–solder interface, but also caused the stress recovery peak. Thus, the combined effect of assembly materials in the die-attach structure should be considered when exploring the joint thermal stresses.

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Section: Effects Of Modeling Scopementioning

confidence: 95%

Section: Effects Of Substratesmentioning

confidence: 99%