A Novel Metal Dielectric Metal Based GAA-Junction-Less TFET Structure for Low Loss SRAM Design

Agarwal, Lucky; Priya, G. Lakshmi; Papnassam, E.; Kumar, Bhavya; Venkatesh, M.

doi:10.1007/s12633-022-02218-0

Cited by 7 publications

(5 citation statements)

References 41 publications

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“…The bitlines have a high value of the capacitive load, which in turn offers RC delays. The recent SRAM designs [ 17 , 18 , 19 , 20 , 21 , 22 , 23 , 24 , 25 , 26 ] reported depict the novel device architectures of 6T SRAM with FinFET, Memristor, and Junctionless TFETs, to claim it to be a low-power device. Here, with our proposed sense amplifier design, the power reduction techniques like negative wordline and source biasing were combined and utilized.…”

Section: Proposed Sense Amplifier: Results and Discussionmentioning

confidence: 99%

Novel Low Power Cross-Coupled FET-Based Sense Amplifier Design for High-Speed SRAM Circuits

et al. 2023

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We live in a technologically advanced society where we all use semiconductor chips in the majority of our gadgets, and the basic criterion concerning data storage and memory is a small footprint and low power consumption. SRAM is a very important part of this and can be used to meet all the above criteria. In this study, LTSpice software is used to come up with a high-performance sense amplifier circuit for low-power SRAM applications. Throughout this research, various power reduction approaches were explored, and the optimal solution has been implemented in our own modified SRAM design. In this article, the effect of power consumption and the reaction time of the suggested sense amplifier were also examined by adjusting the width-to-length (W/L) ratio of the transistor, the power supply, and the nanoscale technology. The exact amount of power used and the number of transistors required by different approaches to better comprehend the ideal technique are also provided. Our proposed design of a low-power sense amplifier has shown promising results, and we employ three variations of VLSI power reduction techniques to improve efficiency. Low-power SRAMs embrace the future of memory-centric neuromorphic computing applications.

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Section: Proposed Sense Amplifier: Results and Discussionmentioning

confidence: 99%

Novel Low Power Cross-Coupled FET-Based Sense Amplifier Design for High-Speed SRAM Circuits

et al. 2023

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“…16 From the obtained results the look-up tables are generated. By utilizing look-up tables and Verilog-A platform the p-MOS and n-MOS FETs are created in CADENCE simulator [26][27][28][29][30][31] and used in the schematics. Figure 11a Figures 11c and 11d depicts the CS amplifier gain for various supply voltages at L G = 16 nm, NS W = 10 nm, and NS H = 5 nm.…”

Section: The Ns-fet Circuit Analysismentioning

confidence: 99%

Common Source Amplifier and Ring Oscillator Circuit Performance Optimization Using Multi-Bridge Channel FETs

Sreenivasulu

Neelam

Vakkalakula

et al. 2023

ECS J. Solid State Sci. Technol.

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Direct current, analog/radio frequency device, and circuit applications of nanosheet (NS) field effect transistors were investigated. To enhance power performance, co-optimization geometry parameters like NS width (NSW) and NS thickness (NSH) are varied for high-performance and low-power applications. A rise of 1.47x in ION and a rise of 5.8x in IOFF is noticed with an increase in NSH due to enlarged effective width (Weff). In addition, a rise of 3.8x in ION and a fall of 76.4% in IOFF is noticed with higher NSW. Larger NSW ensures better transconductance, transconductance generation factor, cut-off frequency, gain-band width product, transconductance frequency product, and intrinsic delay. The optimized supply voltage for maximum voltage gain of common source amplifier and three stage ring oscillators (RO) with varied NSW was performed. The impact of number of stages (N) of three stage RO for better frequency of oscillations was studied for high-frequency circuit applications.

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“…M–Memristor; T–Transistor. Similar works have also been carried out for the implementation of look up tables in PROM circuits using double-gated Memristors and MOS transistors [ 25 , 26 , 27 ].…”

Section: Implementation Of 6t-sram Using Cmos Finfet and Memristormentioning

confidence: 99%

Hybrid Silicon Substrate FinFET-Metal Insulator Metal (MIM) Memristor Based Sense Amplifier Design for the Non-Volatile SRAM Cell

et al. 2023

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Maintaining power consumption has become a critical hurdle in the manufacturing process as CMOS technologies continue to be downscaled. The longevity of portable gadgets is reduced as power usage increases. As a result, less-cost, high-density, less-power, and better-performance memory devices are in great demand in the electronics industry for a wide range of applications, including Internet of Things (IoT) and electronic devices like laptops and smartphones. All of the specifications for designing a non-volatile memory will benefit from the use of memristors. In addition to being non-volatile, memristive devices are also characterized by the high switching frequency, low wattage requirement, and compact size. Traditional transistors can be replaced by silicon substrate-based FinFETs, which are substantially more efficient in terms of area and power, to improve the design. As a result, the design of non-volatile SRAM cell in conjunction with silicon substrate-based FinFET and Metal Insulator Metal (MIM) based Memristor is proposed and compared to traditional SRAMs. The power consumption of the proposed hybrid design has outperformed the standard Silicon substrate FinFET design by 91.8% better. It has also been reported that the delay for the suggested design is actually quite a bit shorter, coming in at approximately 1.989 ps. The proposed architecture has been made significantly more practical for use as a low-power and high-speed memory system because of the incorporation of high-K insulation at the interface of metal regions. In addition, Monte Carlo (MC) simulations have been run for the reported 6T-SRAM designs in order to have a better understanding of the device stability.

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A Novel Metal Dielectric Metal Based GAA-Junction-Less TFET Structure for Low Loss SRAM Design

Cited by 7 publications

References 41 publications

Novel Low Power Cross-Coupled FET-Based Sense Amplifier Design for High-Speed SRAM Circuits

Novel Low Power Cross-Coupled FET-Based Sense Amplifier Design for High-Speed SRAM Circuits

Common Source Amplifier and Ring Oscillator Circuit Performance Optimization Using Multi-Bridge Channel FETs

Hybrid Silicon Substrate FinFET-Metal Insulator Metal (MIM) Memristor Based Sense Amplifier Design for the Non-Volatile SRAM Cell

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