A Novel Low Power Ternary Multiplier Design using CNFETs

Sirugudi, Harita; Gadgil, Sharvani; Vudadha, Chetan

doi:10.1109/vlsid49098.2020.00022

Cited by 13 publications

(12 citation statements)

References 11 publications

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“…The proposed 1-trit multiplier's delay is 18%, 36%, 42%, and 54%, less than that of [14], [16], [20], and [18], respectively. The proposed circuit's average power consumption is about 84%, 90%, and 91% better than [16], [19], and [20] designs, respectively, but it is 10% and 50% higher than [18] and [14]'s circuits, respectively. Also, the proposed design's static power is less than other designs, which can reduce the average power consumption at lower frequencies.…”

Section: Simulation Results and Comparisonsmentioning

confidence: 91%

“…Thus depending on the more dominant power dissipation term, different performance factors will be observed. [14] and [18] have better power dissipation because of the lack of a dynamic precharging circuit. However, as it is evident from the results, since logic gates with pre-charge structures can reduce the number of transistors in the critical path, the proposed design will show better delay performance than [14] and [18].…”

Section: Simulation Results and Comparisonsmentioning

confidence: 99%

“…One of the most popular methods for implementing a ternary half adder and a ternary 1-trit multiplier circuit is to use multiplexers. For example, the designs presented in [14], [15], and [18] are reviewed here. In [14], the input signals are decoded; the use of each decoder adds 10 transistors.…”

Section: Review Of Ternary Logic Design and Previous Workmentioning

confidence: 99%

“…A number of ternary logic computational circuits are given in [11][12][13][14][15][16][17][18][19][20][21][22]. A multiplexer-based ternary half adder and a 1-trit multiplier are presented in [14].…”

Section: Introductionmentioning

confidence: 99%

“…A 1-trit multiplier is also proposed using two types of 2:1 multiplexers in [18]. In [19] and [20], ternary gates have been designed without using the VDD/2 voltage source, and subsequently, Ternary Half Adder (THA) and Ternary 1-trit Multiplier (TMUL) circuits are implemented using the input decoding method and subsequent binary and ternary gates.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

CNFET-based design of efficient ternary half adder and 1-trit multiplier circuits using dynamic logic

Sardroudi

Habibi

Moaiyeri

2021

Microelectronics Journal

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This paper presents a ternary half adder and a 1-trit multiplier using carbon nanotube transistors.The proposed circuits are designed using pass transistor logic and dynamic logic. Ternary logic uses less connections than binary logic, and less voltage changes are required for the same amount of data transmission. Carbon nanotube transistors have advantages over MOSFETs, such as the same mobility for electrons and holes, the ability to adjust the threshold voltage by changing the nanotube diameter, and less leakage power. The proposed half adder has lower power consumption, delay, and fewer transistors compared to recent ternary half adders that use similar design methods. The proposed 1-trit multiplier also has a lower delay than other designs.Moreover, these advantages are achieved over a wide supply voltage range, operating

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Section: Simulation Results and Comparisonsmentioning

confidence: 91%

Section: Simulation Results and Comparisonsmentioning

confidence: 99%

Section: Review Of Ternary Logic Design and Previous Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

CNFET-based design of efficient ternary half adder and 1-trit multiplier circuits using dynamic logic

Sardroudi

Habibi

Moaiyeri

2021

Microelectronics Journal

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Energy Efficient Ternary Multi-trit Multiplier Design Using Novel Adders

Vendhan,

Ahmed,

Gurunarayanan

2024

Circuits Syst Signal Process

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Ant Lion Optimizer for Suppression of Ambipolar Conduction in Schottky Barrier Carbon Nanotube Field Effect Transistors

Kumar

Agrawal

2021

Silicon

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A mathematical model and experimental analysis of the effect of oxide thickness on ambient conduction is provided in the Schottky Barrier Carbon Nanotubes (CNTs) Field Effect Transistor (SB-CNTFET). To develop them as the future of IC (integrated circuit) technology, the suppression of ambipolar behaviour in SB-CNTFET is imperative. The ambipolar nature of SB-CNTFET contributes to a high amount of leakage current. tox ≈ 49.91mm uses a dielectric of gate oxide with a thickness to inhibit the ambipolar behaviour. In an SB-CNTFET, the conductance is regulated by the electrical field at the source/drain contacts and the band bending length at the contacts is determined by t ox . Therefore, the prime parameter t ox that affects the Schottky barrier width and the subthreshold area. The suppression of ambipolar property is presented through experimental analysis. The SB-CNTFET is produced using high-k dielectrics such as Zirconium dioxide. This work discusses the suppression of ambipolar activity in SB-CNTFETs without reducing the I on current using an appropriate dielectric with optimum thickness.

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A Novel Low Power Ternary Multiplier Design using CNFETs

Cited by 13 publications

References 11 publications

CNFET-based design of efficient ternary half adder and 1-trit multiplier circuits using dynamic logic

CNFET-based design of efficient ternary half adder and 1-trit multiplier circuits using dynamic logic

Energy Efficient Ternary Multi-trit Multiplier Design Using Novel Adders

Ant Lion Optimizer for Suppression of Ambipolar Conduction in Schottky Barrier Carbon Nanotube Field Effect Transistors

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