A novel low‐power gate driver architecture for large 8 K 120 Hz liquid crystal display employing IGZO technology

Abstract

A novel low-power gate driver architecture was developed for large 8 K 120 Hz liquid crystal display panel. For this application, not only high-speed driving but also low power consumption is required. We employed a high mobility In-Ga-Zn-O, dual V GL level driving method, and gate driver circuit driven by DC supply. The simulation results show that our proposals meet 8 K 120 Hz driving requirements. Also, we have fabricated a prototype panel and confirmed both high-speed driving and low power consumption. FIGURE 4 -Timing chart (four-phase clock). Journal of the SID 26/5, 2018 305 FIGURE 7 -Block diagram of the shift register.

Foveated imaging by polarization multiplexing for compact near‐eye displays

“…In addition, it would be extremely challenging to render high‐resolution images and videos in real time, and a more efficient image rendering pipeline must also be developed to support tremendous data transfer. Therefore, foveated imaging becomes a more favorable solution to provide ultra‐high‐resolution images by considering the panel fabrication and data transport difficulties 7–12 . Due to the 1‐arcmin requirement being only for the narrow central region (< ±5°) defined by the cone cell distribution on retina, we may only need to provide high resolution for central fovea region instead of the entire field of view 13 .…”

Foveated imaging for near-eye displays

“…Thanks to the tremendous efforts of panel manufactures [4][5][6][7][8][9], the VR display resolution has been pushed to around 4K × 4K recently [4], although there is still a long way to go for lowcost mass production. In addition, the new driving circuitry designs are also required [9,10] due to the much shorter addressing time for each scan line. Even if such a high-resolution panel can be fabricated and successfully driven, there still exists other issue regarding the display data transport [3,4].…”

A metal oxide TFT gate driver with a single negative power source employing a boosting module

“…The voltage of one source is set to be lower than the other one for completely shutting off the pull-down TFTs of the output module. Various integrated gate drivers with double negative power sources have been reported [10][11][12][13]. Double negative power sources, however, will increase the complexity of signal connections with a timing controller, and will result in higher power consumption because of the larger voltage range.…”

“…Double negative power sources, however, will increase the complexity of signal connections with a timing controller, and will result in higher power consumption because of the larger voltage range. The capacitor coupling effect is often used in gate driver circuit design [8][9][10][11][12][13]. The voltage at the internal key nodes is boosted by the capacitor coupling effect, thereby reducing the leakage current [12,13].…”