A novel integrated amorphous silicon TFT gate driver circuit with optimized design for TFT-LCD display panel manufacturing

Lo, I-Hsiu; Cheng, Hui-Wen; Li, Yiming; Lin, Pole-Shang; Shen, Cheng-Han

doi:10.1109/asqed.2011.6111757

Cited by 2 publications

(2 citation statements)

References 14 publications

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“…Therefore, the larger voltage difference (V gh -V gl ') between the Out_1 and CLK1 cause the shorter fall time of the output. In earlier researches [6,7], the applied clocks were analogous to the clocks introduced in Fig. 3(b) as the conventional signals.…”

Section: A Driving Methodsmentioning

confidence: 99%

“…Even the application of the mobile devices, such as the tablet computer, the common resolution is gradually changing to the high definition (HD) or the FHD. Furthermore, the gate driver circuits embedded in display panel becomes worthy and researchable in the FPD design [1][2][3][4][5][6][7][8]. However, a-Si:H thin film transistors are unstable and suffer from an electric field induced threshold voltage shift [9][10][11][12][13].…”

Section: Introductionmentioning

confidence: 99%

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A Novel Driving Method for High-Performance Amorphous Silicon Gate Driver Circuits in Flat Panel Display Industry

Chiang

2016

J. Display Technol.

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In this work, we report a novel driving method to operate the amorphous silicon gate (ASG) driver circuits in flat panel display (FPD). The principal modification is to change the type of the clock signals to two low levels in the ASG circuit. The proposed ASG driver circuit has been implemented using a 5-mask amorphous silicon process for thin film transistors. The fall time of the output in the tested ASG circuit with the novel driving method is about 30% shorter than that with the conventional driving method. Moreover, the minimum operation high voltage keeps the same level of the ASG circuit with the new clock driving. Notably, the proposed driving method causes merely 5.5% increment of the power consumption, compared with the conventional one.Index Terms-amorphous silicon gate driver, fall time, driving method, clock, minimum operation high voltage, performance, power, flat panel display.

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Section: A Driving Methodsmentioning

confidence: 99%