A Novel Highly-Efficient Inexact Full Adder Cell for Motion and Edge Detection Systems of Image Processing in CNFET Technology

Abstract

In this paper, a novel and highly efficient inexact Full Adder cell by exploiting two logic styles including conventional CMOS (C-COMS) and pass transistor logic (PTL) are presented. The so-called carbon nanotube field-effect transistor (CNFET) technology is used to implement circuits at the transistor level. To justify the efficiency of our design, extensive simulations are performed at the transistor level as well as application level. Transistor-level simulations which are carried out by the HSPICE 2008 tool, demonstrate at least 12% higher performance in terms of power-delay-area product (PDAP) of the proposed circuit compared to the latest designs. At the application level, by using the MATLAB tool, inexact Full Adders are employed in the structure of the ripple carry adder (RCA) that is applied in motion and edge detection algorithms. Computer simulation results confirm the appropriate quality of the output images in terms of the peak signal-to-noise ratio (PSNR) and structural similarity (SSIM) criteria. At last, to make a compromise between hardware and application level parameters, the power-delay-area-1/PSNR product (PDAPP) and power-delay-area-1/SSIM product (PDASP) are considered as figures of merit. The proposed circuit shows remarkable improvement from the PDAPP and PDASP points of view compared to its counterparts.

A Novel High-Speed and Low-PDP Approximate Full Adder Cell for Image Blending

“…Upon examination of Table 4, it can be concluded that the suggested cell exhibits superior performance in regard to delay, PDP and EDP metrics across all supply voltages in comparison to its counterparts. As an illustrative example, at 1 V VDD, the suggested cell has 49%, 29%, 19%, 31%, 42%, 17%, 18% and 19% less delay and 52%, 81%, 79%, 24%, 37%, 79%, 7% and 35% less PDP in comparison to [13], [14] (13T), [14] (9T), [15], [17], [18], [19] and [20], respectively. Simulated circuits are tested in the range of 0.8 V to 1 V VDD at 25 • C and 1 GHz at FO4 load to evaluate performance against different power supplies.…”

“…As expected, circuits with non-full swing nodes perform unacceptably against large loads. As an illustrative example, at FO8, the suggested cell has 60%, 18%, 10%, 42%, 48%, 5%, 27% and 39% less delay and 61%, 52%, 48%, 32%, 41%, 50%, 45% and 16% less PDP in comparison to [13], [14] (13T), [14] (9T), [15], [17], [18], [19] and [20], respectively. It is crucial to examine the circuit performance under varying output loads.…”

“…As an illustrative example, at FO8, the suggested cell has 60%, 18%, 10%, 42%, 48%, 5%, 27% and 39% less delay and 61%, 52%, 48%, 32%, 41%, 50%, 45% and 16% less PDP in comparison to [13], [14] (13T), [14] (9T), [15], [17], [18], [19] and [20], respectively. [14] (13T), [14] (9T), [15], [17], [18], [19] and [20].…”

“…PDP and EDP of the presented Full Adder remain almost constant without any significant changes. [13], [14] (13T), [14] (9T), [15], [17], [18], [19] and [20].…”

“…There are eight transistors in the inexact circuit in [19], four of which are located on the critical path. Unlike Cout, the SUM signal is full-swing in this circuit.…”