A novel, high performance and power efficient implementation of 8&amp;#x00D7;8 multiplier unit using MT-CMOS technique

Rajput, Navya; Sethi, Manan; Dobriyal, Paanshul; Sharma, K. G.; Sharma, Geetanjali

doi:10.1109/ic3.2013.6612187

Cited by 6 publications

(6 citation statements)

References 11 publications

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“…The main advantage is that this sutra is simple and saves time while solving the problem. It can be utilized multiplications of 2*2, 3*3 and B*B upto N*N bit [5][6] [14].…”

Section: Aurdhva Triyabhyammentioning

confidence: 99%

An Efficient Architecture of Vedic Multiplier using FinFet Based Pass Transistor Logic

Paulchamy,

Kalpana,

Jaya

2020

IJEAT

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Multiplies is an important component in Digital Signal Processing (DSP) and communication systems. It is utilized in signal and image processing applications including convolution, Fast Fourier Transform (FFT) and correlation. Therefore, it is necessary to develop a multiplier with power efficient and speed to reduce the cost of the system. Vedic multiplier has been introduced to solve the problems of existing multiplier. It is based on 16 algorithms. These algorithms use algebra, arithmetic operations and geometry. Urdhva Tiryabhyam is widely employed formula which provides high speed and efficient. Vedic multiplies generates partial sums and products in single step. It has been designed using pass transistor logic which reduces the number of components utilized to build logic gates by removing unwanted transistors. This paper design a vedic multiplier with FinFET based pass transistor logic. The developed multiplies provides better performance and suitable for high speed applications. 2x2 and 4x4 vedic multipliers are developed and executed 180nm approach with Tanner EDA Tool 3.0.

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“…The main advantage is that this sutra is simple and saves time while solving the problem. It can be utilized multiplications of 2*2, 3*3 and B*B upto N*N bit [5][6] [14].…”

Section: Aurdhva Triyabhyammentioning

confidence: 99%

An Efficient Architecture of Vedic Multiplier using FinFet Based Pass Transistor Logic

Paulchamy,

Kalpana,

Jaya

2020

IJEAT

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“…Here, both Partial product generation and addition is performed concurrently. Hence, it is adaptive to parallel processing [4].…”

Section: Vedic Mathematics 41 Vedic Sutra (Rules)mentioning

confidence: 99%

“…The 8x8 bit Vedic multiplier can be implemented by using four 4×4 bit Vedic multiplier modules [4]. The input bits are (a7-a0) and (b7-b0) the resulting multiplication's 16 bits output will be bits (s15-s0).…”

Section: ×8 Vedic Multiplier (Mtcmos)mentioning

confidence: 99%

“…Multiplication algorithms differ in terms of partial product generation and partial product addition to produce the final result [3]. Multiplication requires carry propagation from the least significant bit (LSB) to the most significant bit (MSB) during the addition of binary partial products thus the latency incurred is during the addition and subtraction of the binary products formed after multiplication [4].Vedic mathematics is the ancient methodology of Indian mathematics which has a unique technique of calculations based on 16 sutras (Formulas). A high speed multiplier design using Vedic Mathematics principals is presented in this paper.…”

Section: Introductionmentioning

confidence: 99%

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Low Power High Speed Multiplier Design based on MTCMOS Technique

Oza¹,

Kadam²

2016

CAE

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The need for devices that consume minimum amount of power was a major driving force behind the development of CMOS technologies. Reduction of power consumption makes a device more reliable. As a result, CMOS devices are best known for low power consumption. Most research on the power consumption of circuits has been focused on the switching power and the power dissipated by the leakage current has been comparatively minor area. Today, every designer either analog circuit or a digital circuit designer is concerned about the amount of power consumption in the circuit at the end. Multi-threshold CMOS is becoming a trendy circuit design technique for low power, high performance application. The paper briefs the implementation of a novel CMOS 8 bit Vedic Multiplier using MTCMOS.

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“…[1][2][3][4].So to overcome this issues Wallace multiplier is designed and it is faster than a simple array multiplier because of its non linearity but Wallace trees are often avoided by designers and compare to other multiplier like array, the Wallace multiplier Vedic multiplier is quicker and consumes lesser power -Ref. [5][6][7][8][9]‖. Power conservation is a key concern in the VLSI circuit design so here low power technique Multi-Threshold Voltage CMOS (MTCMOS) is applied so efficient power management is achieved -Ref.…”

Section: Introductionmentioning

confidence: 99%

Design and Performance Analysis of Multipliers using Different Logic Styles

Bonpapa¹,

Reddy²

2015

IJERT

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A multiplier is one of the chief hardware blocks in most digital and high concert systems such as microprocessors, digital signal processors, etc. In this paper 4×4 as well as 8×8 Array, Wallace and Vedic multipliers structural design is being designed. Among these three types of multipliers Vedic multiplier base on Vedic arithmetic using Urdhva-Tiryabhyam sutra are proved to be the most efficient in terms of lower power consumption. In MOSFET by applying a shrinking technology below 100nm becomes a key challenge for power chip management so to overcome these limitations the CNTFET are introduced, and due to this comparison of multipliers are made between MOSFET 32nm and CNTFET 32nm technology. The CNFET-based multipliers have higher speed, and low power dissipation and it nearly reduces 99% PDP (power-delay product) as compared to the MOSFET. And still to reduce the power consumption the low power technique such as MTCMOS is used and all the three different designs of 4×4 as well as 8x8 multipliers are designed using the Multi-Threshold Voltage CMOS (MTCMOS) it proved to be best among all the implementations. And it nearly reduces 50% of power compare to normal multipliers (i.e. without applying technique). The functionality of all the three designs is based on 32nm Berkeley Predictive Technology Model (BPTM) are calculated at 1v supply voltage and simulating them with hi-spice software.

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A novel, high performance and power efficient implementation of 8×8 multiplier unit using MT-CMOS technique

Cited by 6 publications

References 11 publications

An Efficient Architecture of Vedic Multiplier using FinFet Based Pass Transistor Logic

An Efficient Architecture of Vedic Multiplier using FinFet Based Pass Transistor Logic

Low Power High Speed Multiplier Design based on MTCMOS Technique

Design and Performance Analysis of Multipliers using Different Logic Styles

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