A novel hetero-material gate (HMG) MOSFET for deep-submicron ULSI technology

Zhou, Xing; Long, Wei

doi:10.1109/16.735743

Cited by 97 publications

(11 citation statements)

References 7 publications

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“…The proposed device can be fabricated using various techniques. In literature, some techniques have been suggested to fabricate DGTFETs and DM-DGTFETs [15], [21]- [27] and some techniques have been employed to fabricate the DMG structures [28]- [30]. Due to the structural similarity, the proposed devices can also be fabricated by adapting these techniques.…”

Section: A Device Fabricationmentioning

confidence: 99%

Realizing XOR and XNOR Functions Using Tunnel Field-Effect Transistors

Garg

Saurabh

2020

IEEE J. Electron Devices Soc.

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Recently, a few compact logic function realizations such as AND, OR, NAND and NOR have been proposed using double-gate tunnel field-effect transistor (DGTFET) with independent gate-control. In this paper, using two-dimensional device simulations, we propose to realize the exclusive-OR (XOR) and exclusive-NOR (XNOR) logic functions. To implement an XOR function, a dual-material DGTFET (DM-DGTFET) is used. The structure is designed such that the band-to-band tunneling (BTBT) occurs at the boundary of these dual-material gates, rather than at the source-channel junction. Further, to realize the XNOR function, the gate-source and the gate-drain overlaps are used. The proposed DGTFET-based logic function implementations are able to modulate the current flow as per the required functionality, achieving an ON-state current by OFFstate current (ION /IOF F) ratio of order ∼ 10 9. Furthermore, it is demonstrated that a CMOS-type XNOR gate can be realized by combining the proposed XNOR and XOR functions in the pull-up and pull-down network, respectively.

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Section: A Device Fabricationmentioning

confidence: 99%

Realizing XOR and XNOR Functions Using Tunnel Field-Effect Transistors

Garg

Saurabh

2020

IEEE J. Electron Devices Soc.

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“…Gate engineering is one of the promising solutions to reduce the hot carrier effect and thus increase the lifetime of the device. MOSFET device structures including TFT, FinFET, nanowires that employ gate material engineering [8] improve transport efficiency in the gate by adjusting the pattern of electric field and the surface potential along the channel, which results in improved carrier transport efficiency, better transconductance and also clampdown of SCEs. [9] explains the dual material gate in FET, which employs gate-material engineering, i.e.…”

Section: Introductionmentioning

confidence: 99%

Simulation and Performance Analysis of a Triple-material Gate GAA SNSTFT

Sampson¹,

Sivakumar²,

Velmurugan³

2020

J. Nano- Electron. Phys.

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A Stacked Nano Sheet Gate All Around Thin Film Transistor (SNS GAATFT) with Triple Material (TM) has been proposed in this paper. The TM of the Thin Film Transistor (TFT) is varied by applying three different work functions (WFs) by having different gate materials being used. The transistor considered here for implementation is a p-channel device. The analysis has been carried out using the physical model: temperature-dependent carrier transport model (DD). Mobility Model (MM) includes the effects of doping concentration and electric field, Bandgap Narrowing Model (BNM) and Shockley-Read-Hall recombination Model (SRM) are for carrier lifetime. Synopsys Sentaurus TCAD has been used for the simulation of the proposed model and thus analyzing its characteristics. The characteristics of the proposed TM have been compared to those of the previously proposed Single Material (SM) SNS GAATFT model. For the proposed model, the first and third WFs were kept constant while the WF of the middle region varied between the first and third WFs. The output characteristics analyzed proved a better result for WF values closest to the third WF. Thus, a higher value of the middle WF was used in determining the different characteristics. From the characteristics it can be analyzed that due to varying electric potentials on the gate terminal due to varying WF, the influence of high-speed moving electron is reduced from the source side, and this helps in improving the carrier transport efficiency and thus, it is clear, this, in turn, helps in lowering the hot carrier effects. The comparison result shows that drain current in a TM is found to be almost 4 times higher than that of a SM model which shows better improvement in ION current.

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“…Moreover, the dual-material gate achieves simultaneous suppression of SCE. 17,18) Nonetheless, whether a metal can be used as the gate of MOSFETs is not only determined by its work function. It should meet the basic requirements such as thermal stability and process compatibility with dielectric deposition.…”

Section: Introductionmentioning

confidence: 99%

Analytical Modeling and Simulation of Dual-Material Surrounding-Gate Metal–Oxide–Semiconductor Field Effect Transistors with Single-Halo Doping

Zhang

Jiang

2009

jjap

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We present a modified surrounding-gate metal-oxide-semiconductor field effect transistor (MOSFET), in which the gate consists of two metals with different work functions, and single-halo doping is added to the channel near the source end. The performance of the modified structure was studied by developing physics-based analytical models for the surface potential, electric field, and threshold voltage. It is shown that the novel MOSFET could significantly reduce threshold voltage roll-off and drain-induced barrier lowering, and simultaneously improve carrier transport efficiency by carefully configuring the halo doping and work functions of the dual-material gate. The results predicted using the models are compared with those obtained with the three-dimensional simulator Davinci to verify the accuracy of the proposed analytical models.

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A novel hetero-material gate (HMG) MOSFET for deep-submicron ULSI technology

Cited by 97 publications

References 7 publications

Realizing XOR and XNOR Functions Using Tunnel Field-Effect Transistors

Realizing XOR and XNOR Functions Using Tunnel Field-Effect Transistors

Simulation and Performance Analysis of a Triple-material Gate GAA SNSTFT

Analytical Modeling and Simulation of Dual-Material Surrounding-Gate Metal–Oxide–Semiconductor Field Effect Transistors with Single-Halo Doping

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