A Novel Hardware-Accelerated Priority Queue for Real-Time Systems

Kohútka, Lukáš; Nagy, Lukáš; Stopjaková, Viera

doi:10.1109/dsd.2018.00023

Cited by 6 publications

(13 citation statements)

References 5 publications

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“…The attributes of the MIN queue are described from the hardware as well as real-time computing points of view. These attributes and their requirements are [33,34] Several architectures for data sorting in MIN/MAX queues have been developed, and can be used for task scheduling of realtime systems. Nevertheless, they suffer from scalability issues due to increasing critical path length and resource cost with regards to increasing capacity of schedulers (i.e.…”

Section: Related Work On Min/max Queuesmentioning

confidence: 99%

“…the cells filled with an item) is balanced. The tree balancing feature is very common for binary trees in informatics theory too [33,34].…”

Section: Ready Queue Modulementioning

confidence: 99%

“…This is achieved by implementation of an efficient hardware-based data sorting in a form of MIN/MAX queues, which requires reduced amount of logic resources needed. For this purpose, a new architecture called Heap Queue was developed in order to increase the scalability of data sorting implemented in hardware so that more items can be efficiently sorted [33,34]. This architecture is suitable for usage in task scheduling for real-time systems, where the overall resource costs of the scheduling were significantly reduced too.…”

Section: Introductionmentioning

confidence: 99%

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Novel efficient on-chip task scheduler for multi-core hard real-time systems

Kohútka

Stopjaková

2020

Microprocessors and Microsystems

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This article presents an efficient hardware architecture of EDF-based task scheduler, which is suitable for hard real-time systems due to the constant response time of the scheduler. The proposed scheduler contains a queue of ready tasks that is based on a new MIN/MAX queue architecture called Heap Queue, which is inspired by Shift Registers, Systolic Arrays, heapsort algorithm, the Rocket Queue architecture and dualport RAMs. The instructions of the proposed scheduler have throughput of one instruction per two clock cycles regardless of the actual number of tasks managed by the scheduler, and regardless of the scheduler capacity. The developed task scheduler is optimized for low chip area costs, which leads to lower energy consumption. The Heap Queue-based architecture has constant time complexity due to two clock-cycle response time of the instructions and therefore, the architecture is highly deterministic. The scheduler supports CPUs that can execute 1, 2 or 4 tasks simultaneously, and contains an implementation of clever and efficient logic that can handle conflicts caused by the fact that the scheduler is used by all CPU cores at the same time. The proposed scheduler was verified through SystemVerilog UVM-like simulations that applied billions of randomly generated test instructions. Achieved ASIC (28 nm) and FPGA synthesis results are presented and compared. More than 86% of the chip area and 93% of the total power consumption can be saved if Heap Queue architecture is used in hardware implementations of EDF algorithm. Advantages and disadvantages of the proposed task scheduler are discussed through the comparison to the existing solutions.

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Section: Related Work On Min/max Queuesmentioning

confidence: 99%

“…the cells filled with an item) is balanced. The tree balancing feature is very common for binary trees in informatics theory too [33,34].…”

Section: Ready Queue Modulementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Novel efficient on-chip task scheduler for multi-core hard real-time systems

Kohútka

Stopjaková

2020

Microprocessors and Microsystems

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“…The research work reported in Tabakov and Paznikov 10 presents more specific usage of PQ, where algorithms were designed for PQ selection optimization for insert/ delete operations and for balancing elements in queues. The research work reported in Strzęciwilk et al 11 and Wu et al 12 and the references therein present wide recent research work, mainly in PQ performance analysis using timed Petri Nets in Strzęciwilk et al, 11 and the design and implementation of an adaptive feedback queue algorithm over OpenFlow networks in Wu et al 12 An efficient PQ with a constant response queuing time hardware architecture was presented in Kohutka et al 13 and it was proved that it is applicable in realtime systems. Real-time research on more queuing algorithms was carried out in Proskochylo et al 14 which investigated the real-time traffic QoS behavior, under the queuing algorithms in the process of load balancing.…”

Section: Introductionmentioning

confidence: 99%

“…An efficient PQ with a constant response queuing time hardware architecture was presented in Kohutka et al 13 and it was proved that it is applicable in real-time systems. Real-time research on more queuing algorithms was carried out in Proskochylo et al 14 which investigated the real-time traffic QoS behavior, under the queuing algorithms in the process of load balancing.…”

Section: Introductionmentioning

confidence: 99%

Review and performance evaluation of FIFO, PQ, CQ, FQ, and WFQ algorithms in multimedia wireless sensor networks

Attar

Khosravi

Igorovich

et al. 2020

International Journal of Distributed Sensor Networks

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The best service mechanism in multimedia wireless sensor networks can be achieved based on the multimedia traffic flow by developing a proper simulation algorithm process model, to be a trustable indication for real implementations, which is proposed in this article, together with the algorithm model outcome analysis. The quality estimation of the proposed mechanism is investigated by simulating real data transmission and obtaining the integral criterion of the processed mechanism, to determine the queue formation and loading control. Accordingly, it was proved that the first-in first-out algorithm is not useful as a flow algorithm; however, it is regarded as suitable to be considered as the benchmark algorithm when compared with the other algorithms such as priority queue, custom queue, fair queuing, and weighted fair queuing algorithms. Finally, each algorithm’s advantages and disadvantages were verified and the best usage conditions according to certain parameters, such as packet loss probability, average time delay, and jitter, were declared.

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FPGA implementation of hardware accelerated RTOS based on real-time event handling

Zagan

Găitan

2023

J Supercomput

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Actual trends in the real-time system field consists of migration towards complex central processing unit (CPU) architectures with enhanced execution predictability and rapid CPU contexts switch, thus obtaining high-performant control systems. The main objective of this paper is to present the results obtained following the implementation of real-time operating systems (RTOS) functions in hardware. Based on the CPU resource multiplication concept, actual researches has been focused on synthesizing in field-programmable gate array (FPGA) and implementing innovative solutions to improve RTOS performance. The results are materialized by validating an efficient hardware scheduler micro-architecture, from which a remarkable efficiency and a plus of performance and predictability are obtained. The experimental results, the FPGA resource requirements for implementation of the processor in different configurations, and the comparisons with other similar processor architectures are presented in order to verify theoretical aspects proposed through this paper.

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A Novel Hardware-Accelerated Priority Queue for Real-Time Systems

Cited by 6 publications

References 5 publications

Novel efficient on-chip task scheduler for multi-core hard real-time systems

Novel efficient on-chip task scheduler for multi-core hard real-time systems

Review and performance evaluation of FIFO, PQ, CQ, FQ, and WFQ algorithms in multimedia wireless sensor networks

FPGA implementation of hardware accelerated RTOS based on real-time event handling

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