A Novel Framework for Applying Multiobjective GA and PSO Based Approaches for Simultaneous Area, Delay, and Power Optimization in High Level Synthesis of Datapaths

Abstract

High-Level Synthesis deals with the translation of algorithmic descriptions into an RTL implementation. It is highly multiobjective in nature, necessitating trade-offs between mutually conflicting objectives such as area, power and delay. Thus design space exploration is integral to the High Level Synthesis process for early assessment of the impact of these trade-offs. We propose a methodology for multi-objective optimization of Area, Power and Delay during High Level Synthesis of data paths from Data Flow Graphs (DFGs). The technique performs scheduling and allocation of functional units and registers concurrently. A novel metric based technique is incorporated into the algorithm to estimate the likelihood of a schedule to yield low-power solutions. A true multi-objective evolutionary technique, "Nondominated Sorting Genetic Algorithm II" (NSGA II) is used in this work. Results on standard DFG benchmarks indicate that the NSGA II based approach is much faster than a weighted sum GA approach. It also yields superior solutions in terms of diversity and closeness to the true Pareto front. In addition a framework for applying another evolutionary technique: Weighted Sum Particle Swarm Optimization (WSPSO) is also reported. It is observed that compared to WSGA, WSPSO shows considerable improvement in execution time with comparable solution quality.

Application of Evolutionary Algorithms for Multi-objective Optimization in VLSI and Embedded Systems

“…It has been proven that scheduling and binding of DFGs under constraints such as FU allocation is NP-complete, thus necessitating heuristic approaches to arrive at near optimal solutions (Gerez 2000). Early work in behavioral synthesis focused on constructive approaches which schedule one node at a time.…”

“…For example L ¼ 4 for the schedule in Fig. The latter is obtained by determining the total number of registers required for the DFG implementation using the left edge algorithm (Gerez 2000). The area cost A of the schedule is based on the total FUs and registers required to bind all the nodes in the DFG.…”

Swarm‐inspired exploration of architecture and unrolling factors for nested‐loop‐based application in architectural synthesis

“…position of particle velocity of particle dimension (D) solution (S i ) of problem exploration drift #resource types + #UFs Fig. 4 Comparison of QoR and exploration runtime with [4,5] Conclusion: A novel model for delay estimation based on UF has been proposed. Moreover, a novel approach for exploration of an optimal architecture and UF for nested-loop-based CDFGs using swarm intelligence has been presented.…”

“…In [4] evolutionary algorithm-based DSE required manual intervention to decide UF besides considering only UFs which are multiples of iteration count. Harish et al [5] used a genetic algorithm and weighted sum PSO-based DSE which did not consider constraints in cost function and UF during DSE.…”

“…Note: the CDFGs are generated from the VHDL format of the benchmarks given in [6]. In the first graph, the quality of result (QoR) [1] of the proposed approach is compared with [4,5]. It is clear from Fig.…”