A Novel Floating Gate Structure for High-Reliability and High-Speed Flash Application

Abstract

In this paper, a novel flash memory cell structure with the floating gate shaped like the Roman number "I", aiming at increasing the control gate coupling ratio and reducing the interference of flash memory cell in the array, is proposed. Without introducing extra mask and complexity, the process for this structure is self-aligned and fully compatible with standard flash memory process. 3D process and device simulations of the novel structure in comparison with conventional cells have been carried out using Sentaurus TCAD tool. Simulation results show enhanced control gate coupling ratio thanks to the increased ONO layers between control gate and floating gate. In addition, the cross-talking in flash array can be dramatically reduced due to the decrease of contact area between adjacent cells. These advantages indicate that the proposed structure has the potential for lower voltage, high reliability and ultra-scaled flash technology.