A novel efficient TSV built-in test for stacked 3D ICs

Abstract

A through-silicon via (TSV) is established as the main enabler for a three-dimensional integrated circuit (3D IC) that increases system density and compactness. The exponential increase in TSV density led to TSV-induced catastrophic and parametric faults. We propose an original architecture that detects errors caused by TSV manufacturing defects. The proposed design for testability is a built-in technique that detects errors in an early manufacturing stage and is hence very economically attractive. The proposal is capable of testing each and every TSV in the network. The technique achieves high fault coverage and high observability.

Internal defect identification method of TSV 3D packaging based on built-in integrated sensor

“…1–4 Since TSV gradually develops toward smaller sizes, the scale effect is more obvious and the stress mismatch is more serious, resulting in defects such as bottom voids, gaps and filling missing. 5–7 The existence of these defects can adversely affect the performance of electronic devices, reduce the reliability of the device, and even damage the device. As a result, it is critical to develop a method for accurately detecting internal defects.…”

“…(5) The genetic algorithm performs selection, crossover and mutation operations according to the fitness of each individual to obtain a new population P(g + 1), and the evolutionary algebra g = g + 1. (6) Determine whether the maximum evolutionary algebra has been reached, if it has been reached, stop the calculation and return to the individual with the highest fitness; otherwise, go to step (4) until the maximum evolutionary algebra is reached (7). Output the real-valued number corresponding to the individual with the highest fitness, which is the optimal smoothing factor; (8) Establish a GRNN model with the optimal smoothing factor s, make predictions on the test samples, and get the prediction results.…”