A Novel DSP Architecture for Scientific Computing and Deep Learning

Yang, Chao; Chen, Shuming; Zhang, Jian; Lv, Zhao; Wang, Zhi

doi:10.1109/access.2019.2905302

Cited by 14 publications

(4 citation statements)

References 29 publications

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“…DSPs specialize in signal processing applications [7], featuring tailored architectures with dedicated Arithmetic Logic Units (ALUs), parallel processing capabilities, and efficient data pathways. These processors use specific Instruction Set Architectures (ISAs) designed for signal processing, allowing for the streamlined execution of complex algorithms.…”

Section: Existing Workmentioning

confidence: 99%

Accelerating DSP Applications on a 16-Bit Processor: Block RAM Integration and Distributed Arithmetic Approach

Mohanarangam,

M Shirur

et al. 2023

Electronics

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Modern processors have improved performance but still face challenges such as power consumption, storage limitations, and the need for faster processing. The 16-bit Digital Signal Processors (DSPs) accelerate DSP applications by significantly enhancing speed and performance for tasks including audio processing, telecommunications, image and video processing, wireless communication, and consumer electronics. This paper presents a novel technique for accelerating DSP applications on a 16-bit processor by combining two methods: Block Random Access Memory (BRAM) and Distributed Arithmetic (DA). Integrating BRAM as a replacement for conventional RAM minimizes timing and critical route delays, improving processor efficiency and performance. Furthermore, the Distributed Arithmetic approach enhances performance and efficiency by utilizing precomputed lookup tables to expedite multiplication operations within the Arithmetic and Logic Unit (ALU). We use the Xilinx Vivado tool, a robust development environment for FPGA-based systems, for the design process and execute the hardware implementation using the Genesys2 Kintex board. The proposed work produces improved efficiency with a cycle per instruction of 2, where the delay is 2.009 ns, the critical path delay is 8.182 ns, and the power consumption is 4 mW.

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Section: Existing Workmentioning

confidence: 99%

Accelerating DSP Applications on a 16-Bit Processor: Block RAM Integration and Distributed Arithmetic Approach

Mohanarangam,

M Shirur

et al. 2023

Electronics

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“…The second option is a Chinese alternative GPGPU variant, which is accelerator processors developed at the University of Defense Technology of China (NUDT) based on a DSP processor for processing signals like GPDSP FT-Matrix2000 (Chao Y., 2019), FT-Matrix2000 + and FT-Matrix3000 for the planned supercomputer Tianhe-3. These processors are ideologically comparable with the domestic hybrid scalar-vector processor NM6408MP.…”

Section: Development Of Gpgpu Type Accelerator For Scientific and Tecmentioning

confidence: 99%

Main Scientific and Technological Problems in the Field of Architectural Solutions for Supercomputers

Molyakov¹

2020

CIS

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In this paper author describes creation of a domestic accelerator processor capable of replacing NVIDIA GPGPU graphics processors for solving scientific and technical problems and other tasks requiring high performance, but which are characterized by good or medium localization of the processed data. Moreover, this paper illustrates creation of a domestic processor or processors for solving the problems of creating information systems for processing big data, as well as tasks of artificial intelligence (deep learning, graph processing and others). Therefore, these processors are characterized by intensive irregular work with memory (poor and extremely poor localization of data), while requiring high energy efficiency. The author points out the need for a systematic approach, training of young specialists on supporting innovative research.

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“…However, it also presents a new challenge for register allocation. The YHFT-Matrix series DSP [32][33][34] has both a SPU and a VPU. In practical application, the result data in vectors obtained by previous steps may need to be further processed one by one in the following steps, so they need to be transferred from the VPU to the SPU.…”

Section: Introductionmentioning

confidence: 99%

Research on global register allocation for code containing array‐unit dual‐usage register names

Zhang

Wang

et al. 2022

Concurrency and Computation

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Summary Array‐unit dual‐usage register is a kind of register resource that can be read or written as a whole or individually. It is mainly configured in processors with SIMD processing units and provides register‐level speed data transfer between the scalar and vector processing units. To improve the efficiency of algorithms by using an array‐unit dual‐usage register, we investigate in this article the problem of adapting register allocation to code containing array‐unit dual‐usage register names. We propose a corresponding global register allocation method by combining the allocation of regular registers with array‐unit dual‐usage register, ensuring that the names of array‐unit dual‐usage register can be used in the input code of register allocation. Moreover, we present the processing framework of this method and the specific algorithms of some related vital aspects and demonstrate the working principles of the algorithms by an example. Experimental studies were conducted on a platform based on the FT‐M7002 DSP core, and showing that our register allocation method can effectively handle codes containing array‐unit dual‐usage register names and support relevant application algorithms to improve their data transfer scheme. For some typical algorithms with input matrix, substantial performance improvements of twofold or higher are achieved.

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A Novel DSP Architecture for Scientific Computing and Deep Learning

Cited by 14 publications

References 29 publications

Accelerating DSP Applications on a 16-Bit Processor: Block RAM Integration and Distributed Arithmetic Approach

Accelerating DSP Applications on a 16-Bit Processor: Block RAM Integration and Distributed Arithmetic Approach

Main Scientific and Technological Problems in the Field of Architectural Solutions for Supercomputers

Research on global register allocation for code containing array‐unit dual‐usage register names

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