A novel double-π model for multilayer inductor based on 130 nm SiGe process and modified parameter extraction procedure

Member, Ieee Xiuping Li Senior; Cao, Cheng; Yajing, Hou; Liu, Jiangfan; Wang, Zhe; Xia, Qing; Member, Ieee Hua Zhu

doi:10.1080/02726343.2019.1675437

Cited by 1 publication

(1 citation statement)

References 29 publications

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“…So far, extensive research has been conducted on the compact equivalent circuit of the on-chip single-layer spiral inductor. Among them, the single π model [5][6][7] is the most used, except for the 2-π model 1,8,9 and the T-type equivalent model. 10 These compact circuit models can significantly reduce calculation time and are easily combined with circuit amplitude design tools.…”

Section: Introductionmentioning

confidence: 99%

A physical‐based model for on‐chip double‐layer spiral inductors with a ground shield

Yang

Lan

Zhang

et al. 2022

Micro & Optical Tech Letters

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A physical‐based analytical model for double‐layer inductors to reduce the on‐chip area occupied is presented. A simple DC inductance model is developed based on self‐inductance and mutual inductance of metal segments. A new method has been adopted to accurately estimate the nonuniform distribution of currents due to skin and proximity effects, and a ladder structure is used to characterize them. Dielectric and substrate electric effects are analyzed, and a ground shield is used to reduce losses. The effective inductance reduction due to the eddy current in the silicon substrate is modeled by a negative mutual inductance between the metal spiral lines and the substrate. All the model parameters can be calculated from the structure sizes and process parameters. On‐chip inductors with different parameters were fabricated for the verifications. The EM simulated results and measured results are in good agreement with the proposed model. Thus, it is suitable for different technologies. This model can facilitate the design and optimization of on‐chip inductors for RF IC applications.

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