A novel design approach for low pass finite impulse response filter based on residue number system

Maji, Pallab; Rath, Girija Sankar

doi:10.1109/icectech.2011.5941804

Cited by 3 publications

(1 citation statement)

References 11 publications

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“…Scaling was performed in binary via residueto-binary conversion to avoid the overflow of dynamic range. In the latest RNS implementation of a 32-bit low-pass finite impulse response (FIR) filter [3], signed number was represented in sign-magnitude form with its magnitude converted to RNS. This atypical RNS representation of signed integer suffers from the dual zero representations and the need to remap the magnitude for regular addition and Manuscript received April 13, 2012.…”

Section: Introduction Esidue Number System (Rns)mentioning

confidence: 99%

Efficient VLSI Implementation of $2^{{n}}$ Scaling of Signed Integer in RNS ${\{2^{n}-1, 2^{n},2^{n}+1\}}$

Tay

Chang

Low

2013

IEEE Trans. VLSI Syst.

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Scaling is a problematic operation in ResidueNumber System (RNS) but a necessary evil in implementing many digital signal processing (DSP) algorithms for which RNS is particularly good. Existing signed integer RNS scalers entail a dedicated sign detection circuit, which is as complex as the magnitude scaling operation preceding it. In order to correct the incorrectly scaled negative integer in residue form, substantial hardware overheads have been incurred to detect the range of the residues upon magnitude scaling. In this paper, a fast and area efficient 2 n signed integer RNS scaler for the moduli set {2 n 1, 2 n , 2 n +1} is proposed. Complex sign detection circuit has been obviated and replaced by simple logic manipulation of some bit level information of intermediate magnitude scaling results. Comparing with the latest signed integer RNS scalers of comparable dynamic ranges, the proposed architecture achieves at least 21.6% of area saving, 28.8% of speedup and 32.5% of total power reduction for n ranges from 5 to 8.

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Section: Introduction Esidue Number System (Rns)mentioning

confidence: 99%

Efficient VLSI Implementation of $2^{{n}}$ Scaling of Signed Integer in RNS ${\{2^{n}-1, 2^{n},2^{n}+1\}}$

Tay

Chang

Low

2013

IEEE Trans. VLSI Syst.

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Modulo 2<sup>n</sup>−2 arithmetic units

Vassalos

Bakalis

2013

Eurocon 2013

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A Pn Sequence Generator Based On Residue Arithmetic For Multi-User Ds-Cdma Applications

Chithra¹,

Maji²,

Patra³

et al. 2012

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A novel design approach for low pass finite impulse response filter based on residue number system

Cited by 3 publications

References 11 publications

Efficient VLSI Implementation of $2^{{n}}$ Scaling of Signed Integer in RNS ${\{2^{n}-1, 2^{n},2^{n}+1\}}$

Efficient VLSI Implementation of $2^{{n}}$ Scaling of Signed Integer in RNS ${\{2^{n}-1, 2^{n},2^{n}+1\}}$

Modulo 2<sup>n</sup>−2 arithmetic units

A Pn Sequence Generator Based On Residue Arithmetic For Multi-User Ds-Cdma Applications

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A novel design approach for low pass finite impulse response filter based on residue number system

Cited by 3 publications

References 11 publications

Efficient VLSI Implementation of $2^{{n}}$ Scaling of Signed Integer in RNS ${\{2^{n}-1, 2^{n},2^{n}+1\}}$

Efficient VLSI Implementation of $2^{{n}}$ Scaling of Signed Integer in RNS ${\{2^{n}-1, 2^{n},2^{n}+1\}}$

Modulo 2<sup>n</sup>&#x2212;2 arithmetic units

A Pn Sequence Generator Based On Residue Arithmetic For Multi-User Ds-Cdma Applications

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Product

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Modulo 2<sup>n</sup>−2 arithmetic units