A Novel Design and Optimization Approach for Low Noise Amplifiers (LNA) Based on MOST Scattering Parameters and the gm/ID Ratio

Abstract

This work presents a new design methodology for radio frequency (RF) integrated circuits based on a unified analysis of the scattering parameters of the circuit and the gm/ID ratio of the involved transistors. Since the scattering parameters of the circuits are parameterized by means of the physical characteristics of transistors, designers can optimize transistor size and biasing to comply with the circuit specifications given in terms of S-parameters. A complete design of a cascode low noise amplifier (LNA) in MOS 65 nm technology is taken as a case study in order to validate the approach. In addition, this methodology permits the identification of the best trade-off between the minimum noise figure and the maximum gain for the LNA in a very simple way.

A gm/ID-Based Low-Power LNA for Ka-Band Applications

“…The characterization of a MOSFET in terms of / ratio allows the derivation of the main performance metrics of a circuit to provide a width-independent sizing tool, allowing fast optimization and near-first-time successful design. A series of LUTs can be generated to avoid conventional SPICE iterative simulations, and designers can apply optimization algorithms to find optimal sizing and operating points or simply explore the design space more efficiently [ 31 ]. The first step consists of simulating several devices to fully characterize their behavior and build the LUTs with fundamental DC, AC, and noise parameters.…”

Mixed-Variable Bayesian Optimization for Analog Circuit Sizing through Device Representation Learning

“…As shown in Figure 1, the core of this approach is an iterative procedure, which repeats the steps of searching for potentially promising solutions, using optimization algorithms, and evaluating them. Depending on the choice of evaluation engine, these methods are distinguished between simulation-based [20] and model-based ones [21]. The model-based methods evaluate the goodness of each parametrization of the circuit using analytical equations, which are derived by hand analysis.…”

“…A particular example of this family of methods is the transconductance-over-current g m /I d methodology [22], where transistors' behavior is implicitly taken into account by replacing the overdrive voltage with the technology-independent g m /I d metric. By building analytical models of the circuit's performance using the g m /I d as design variable, one may define optimization problems that result in sized circuits, such as in [21]. A limitation of the g m /I d is that, being a small-signal metric that describes the inversion level of each transistor, it does not give insights into the large signal behavior of the circuit.…”

Design of High Stability Factor Lna using Cascade Mosfet at 850MHz Rf Frequency

“…By the sub-threshold region, the single ended(SE) cascode topology is operated and the gain was increased. Mahsa Keshavarz Hedayati et.al [8], In his paper exhibits a plan technique has reduced low noise amplifier(LNA) of 33-GHzfor applications of 5G acknowledged in LP CMOS of 28-nm. In light of the novel arrangement of difficulties displayed by cutting edge nanoscale CMOS, the accentuation is put here on the streamlining of plan and format methods for active and passive components within the sight of thorough metal thickness guidelines and other back-end-of-the-line (BEOL) challenges.Every single passive element of transmission lines, pads and inductors are structured and streamlined with full wave recreations to adapt to the severe metal thickness standards and other referenced BEOL difficulties has innovation for a tasteful mm-wave execution.…”