A novel dead-time compensation strategy of three-level inverter

Abstract

It is necessary to insert a switching delay time in pulse width modulation(PWM) voltage-fed inverters to avoid the short through of phase bridge. This causes well known dead time effect which distorts the output voltage and current. This paper puts forward a new three-level dead-time compensation method, which compensates dead time, turn on and off delay and forward voltage drop.A three-level inverter hardware platform was built based on FPGA and DSP, and the relevant experiment has been done on the 30kW three-phase induction motor. Experimental results verified the feasibility and correctness of the algorithm.