2014 IEEE Conference and Expo Transportation Electrification Asia-Pacific (ITEC Asia-Pacific) 2014
DOI: 10.1109/itec-ap.2014.6940985
View full text
Sign up to set email alerts

Abstract: It is necessary to insert a switching delay time in pulse width modulation(PWM) voltage-fed inverters to avoid the short through of phase bridge. This causes well known dead time effect which distorts the output voltage and current. This paper puts forward a new three-level dead-time compensation method, which compensates dead time, turn on and off delay and forward voltage drop.A three-level inverter hardware platform was built based on FPGA and DSP, and the relevant experiment has been done on the 30kW three… Show more

Help me understand this report

This publication either has no citations yet, or we are still processing them

Set email alert for when this publication receives citations?

See others like this or search for similar articles