A Novel CMOS Full Adder

Navi, Keivan; Kavehie, O.; Rouholamini, M.; Sahafi, Amir; Mehrabi, Shima

doi:10.1109/vlsid.2007.18

Cited by 24 publications

(17 citation statements)

References 17 publications

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“…In general, bridge style can lead to very structured designs. In this style control signals can be applied to the sides of meshes [9], [10]. Figure 2 illustrates a bridge implementation of the three inputs majority function (or carry generator).…”

Section: Bridge Style Cmos Circuitsmentioning

confidence: 99%

“…In order to construct a full-adder, two different parts are required. Carry part implementation has been performed as Figure 2 and sum function can be implemented in a similar manner leads to realization of a full-adder [9], [10]. An implementation of sum function is shown based on the bridge style in Figure 3.…”

Section: Bridge Style Cmos Circuitsmentioning

confidence: 99%

“…The bridge style has been employed for designing full-adders [9]. The [10] introduces bridge CMOS design methodology. Based on the bridge style, an innovative high speed, low power, symmetric and dense CMOS 1-bit full-adder cell has been presented, in this study.…”

Section: Introductionmentioning

confidence: 99%

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Design of Robust and High-Performance 1-Bit CMOS Full Adder for Nanometer Design

Kavehei

Azghadi

Navi

et al. 2008

2008 IEEE Computer Society Annual Symposium on VLSI

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Full-adders are the core element of the complex arithmetic circuits like addition, multiplication, division and exponentiation. Regarding to this importance, new idea and investigations for constructing full-adders are required. As far as related literature is concerned, generality and ease of use, as well as voltage and transistor scaling are considerable advantages of CMOS logic design versus other design style such as CPL specially when cell-based design are targeted. This paper proposes a novel, symmetric and efficient design for a CMOS 1-bit full-adder. Besides, another fully symmetric full-adder has been presented. Results and simulations demonstrate that the proposed design leads to an efficient full-adder in terms of power consumption, delay and area in comparison to a well-known conventional full-adder design. The postlayout simulations have been done by HSPICE with nanometer scale transistors considering all parasitic capacitors and resistors.

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Section: Bridge Style Cmos Circuitsmentioning

confidence: 99%

Section: Bridge Style Cmos Circuitsmentioning

confidence: 99%

See 1 more Smart Citation

Design of Robust and High-Performance 1-Bit CMOS Full Adder for Nanometer Design

Kavehei

Azghadi

Navi

et al. 2008

2008 IEEE Computer Society Annual Symposium on VLSI

Self Cite

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“…Addition is one of the vital and frequently used arithmetic operations in many signal processing and other applications. Bridge transistors design style offers more regularity and higher density than conventional CMOS design style [4]. Adder is one of the most valuable components of a processor which determines its throughput, as it is used in the ALU, and for address generation in case of cache memory [5].…”

Section: Introductionmentioning

confidence: 99%

Relative Performance Analysis of Different CMOS Full Adder Circuits

Suman¹,

Samanta²,

Chowdhury³

et al. 2015

IJCA

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Different adder circuits are elementary blocks in many contemporary integrated circuits, which are not only employed to perform addition operations, but also other arithmetic operations such as subtraction, multiplication and division. Full adder is the basic building block of any adder circuit. Area, speed and power are the three main design metrics for any VLSI circuit. In this work, eight different full adders' circuits based on standard (std.) CMOS, CPL, 16-Transistor, DCVSL, PTL, TGA, 14-Transistor and 8-Transistor have been designed and implemented using Tanner EDA simulation tool. In this paper, authors have compared the propagation delay, power consumption and power delay product (PDP) of different full adder circuits by varying supply voltage (V dd ).

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“…Many studies have been done to reduce area, delay, power, and energy of adder cells. [1][2][3][4][5] Many of these studies have been investigated different topologies to implement the cells with focus on delay-power trade-off without considering process variation. 1,2 As technology is scaling down challenges faced by the designers become more complex.…”

Section: Introductionmentioning

confidence: 99%

High-performance bridge-style full adder structure

et al. 2008

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Adders are the core element in arithmetic circuits like subtracters, multipliers, and dividers. Optimization of adders can be achieved at device, circuit, architectural, and algorithmic levels. In this paper we present a new optimize full adder circuit structure that provides an improved performance compared to standard and mirror types adder structures. The performance of this adder in terms of power, delay, energy, and yield are investigated. This paper also proposes a novel simulation setup for full adder cells that is suitable for analyzing full adder cells at the high frequency. The simulation results of this structure will take into account the process variations for a 90 nm CMOS process and present results based on post-layout simulation using Cadence and Synopsys tools.

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A Novel CMOS Full Adder

Cited by 24 publications

References 17 publications

Design of Robust and High-Performance 1-Bit CMOS Full Adder for Nanometer Design

Design of Robust and High-Performance 1-Bit CMOS Full Adder for Nanometer Design

Relative Performance Analysis of Different CMOS Full Adder Circuits

High-performance bridge-style full adder structure

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