A Novel Clock Gating Approach for the Design of Low-Power Linear Feedback Shift Registers

Abstract

This paper presents an efficient solution to reduce the power consumption of the popular linear feedback shift register by exploiting the gated clock approach. The power reduction with respect to other gated clock schemes is obtained by an efficient implementation of the logic gates and properly reducing the number of XOR gates in the feedback network. Transistor level simulations are performed by using standard cells in a 28-nm FD-SOI CMOS technology and a 300-MHz clock. Simulation results show a power reduction with respect to traditional implementations, which reaches values higher than 30%.INDEX TERMS Complementary pass-transistor logic (CPL), gated clock, linear feedback shift register (LFSR), low-power design, transmission gate (TG)

Reconfigurable linear feedback shift register for wireless communication and coding

“…The serial implementation of a linear feedback shift register [14], [15] is depicted in Figure 2. It is clear from the system behavior that the serial architecture has two drawbacks: first, every clock causes the entire structure to become time-locked, and second, only one information bit is produced.…”