A novel chip-to-wafer (C2W) three-dimensional (3D) integration approach using a template for precise alignment

Chen, Qianwen; Zhang, Dingyou; Xu, Zheng; Beece, Adam; Patti, Robert; Tan, Zhimin; Wang, Zheyao; Liu, Litian; Lü, Jian–Qiang

doi:10.1016/j.mee.2011.04.047

Cited by 18 publications

(7 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In addition, when the existing chips or wafers are stacked, the development schedule is shortened and the manufacturing cost is effectively reduced. The production equipment includes wafer to wafer bonder (Lin and Lee, 2014), chip to wafer bonder (Lee et al, 2011), deep reactive-ion etching, laser (Chen et al, 2011), viafilling tool, mask aligner, electroplating tool, and spray coating tool (Marinov et al, 2013;Lin and Chiu, 2011).…”

Section: Introductionmentioning

confidence: 99%

Optical alignment and compensation control of die bonder for chips containing through-silicon vias

Lin

Hung

Chen

et al. 2019

View full text Add to dashboard Cite

Purpose This study aims to present an optical alignment and compensation control of die bonder for chips containing through-silicon vias and develop three-dimensional integrated circuit stacked packaging for compact size and multifunction. Design/methodology/approach The machine vision, optical alignment method and sub-pixel technology in dynamic imaging condition are used. Through a comparison of reference image, the chip alignment calibration can improve machine accuracy and stability. Findings According to the experimental data and preliminary results of the analysis, accuracy can be achieved within the desired range, and the accuracy is much better than traditional die bonder equipment. The results help further research in die bonder for chips containing through-silicon vias. Originality/value In subsequent testing of the chip, the machine can simultaneously test multiple chips to save test time and increase productivity.

show abstract

Section: Introductionmentioning

confidence: 99%

Optical alignment and compensation control of die bonder for chips containing through-silicon vias

Lin

Hung

Chen

et al. 2019

View full text Add to dashboard Cite

show abstract

“…Therefore, chip-to-wafer stacking can achieve higher throughput than chip-to-chip stacking. In addition, a specially designed template can be used as the carrier to improve the precision of the alignment [12]. In recent years, there have been numerous advances in chip-to-chip and chip-to-wafer approaches, many of which use fine-pitch microbumps or Cu pillars for interconnection and adopt improved underfill dispensing technologies.…”

Section: Introductionmentioning

confidence: 99%

Three-Dimensional and 2.5 Dimensional Interconnection Technology: State of the Art

Liu

Park

2014

Journal of Electronic Packaging

View full text Add to dashboard Cite

Three-dimensional (3D) packaging with through-silicon-vias (TSVs) is an emerging technology featuring smaller package size, higher interconnection density, and better performance; 2.5D packaging using silicon interposers with TSVs is an incremental step toward 3D packaging. Formation of TSVs and interconnection between chips and/or wafers are two key enabling technologies for 3D and 2.5D packaging, and different interconnection methods in chip-to-chip, chip-to-wafer, and wafer-to-wafer schemes have been developed. This article reviews state-of-the-art interconnection technologies reported in recent technical papers. Issues such as bump formation, assembly/bonding process, as well as underfill dispensing in each interconnection type are discussed.

show abstract

“…The advantages include small form factors, high performances, low power consumption, low manufacturing cost, and high-density heterogeneous integration [1][2][3][4]. As a result of these attractive properties, 3D integration has been utilized in the development of novel semiconductor devices.…”

Section: Introductionmentioning

confidence: 99%

Determination of the characteristics of the metallic bonding interface and the bonding strength of a Cu interlayer by using atomic force microscopy

Choi

Cui

Kim

et al. 2014

Journal of the Korean Physical Society

View full text Add to dashboard Cite

We report a low-temperature thermo-compression bonding process that utilizes chemical surface activation and is useful in 3D integration processing of wafers. Cu possesses desirable properties, such as ideal electrical properties, good thermal conductivity, and longer electro-migration times, making it an attractive interlayer material for the 3D integration process. However, in general, a high thermal energy of 400 • C or more is required for Cu-Cu bonding to be successful. In order to address this problem, this investigation sought to confirm chemical activation of a Cu surface during the bonding process by using atomic force microscopy (AFM) to measure the bonding strength. The reliability of AFM has been established in previous research. The bonding strength of the Cu was determined to be about 6.7 J/m 2 at 150 • C. This bonding strength can be used for 3D integration applications, and the possibility of low-temperature thermo-compression was confirmed by chemical surface activation.

show abstract

A novel chip-to-wafer (C2W) three-dimensional (3D) integration approach using a template for precise alignment

Cited by 18 publications

References 5 publications

Optical alignment and compensation control of die bonder for chips containing through-silicon vias

Optical alignment and compensation control of die bonder for chips containing through-silicon vias

Three-Dimensional and 2.5 Dimensional Interconnection Technology: State of the Art

Determination of the characteristics of the metallic bonding interface and the bonding strength of a Cu interlayer by using atomic force microscopy

Contact Info

Product

Resources

About